Commit Graph

209 Commits

Author SHA1 Message Date
Florent Kermarrec 70f1f96fda litescope/drivers: do not build regs when addrmap is None 2015-03-17 16:04:31 +01:00
Florent Kermarrec a266deb58e LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 16:01:25 +01:00
Florent Kermarrec d2cb41bc63 LiteXXX cores: convert port parameter to int if is digit in test/make.py 2015-03-17 15:58:21 +01:00
Florent Kermarrec 2327710387 liteeth/phy/gmii : set tx_er to 0 only if it exits 2015-03-17 12:24:06 +01:00
Florent Kermarrec 408d0fd2dd liteeth: use default programmer in make.py 2015-03-17 12:12:21 +01:00
Florent Kermarrec ec6ae75065 liteeth: use CRG from Migen in base example 2015-03-17 12:11:51 +01:00
Florent Kermarrec a874f85854 litescope: use CRG from Migen 2015-03-17 11:52:54 +01:00
Florent Kermarrec faf185d58d liteeth: make gmii phy generic 2015-03-16 23:04:37 +01:00
Florent Kermarrec d8b59c03a2 litesata: avoid hack on kc705 platform with new mibuild toolchain management 2015-03-14 01:08:36 +01:00
Florent Kermarrec 28d04ec300 soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
Sebastien Bourdeauducq 32676fffd2 soc/sdram: sync with new mibuild toolchain management 2015-03-13 23:19:08 +01:00
Florent Kermarrec c3c7f627d9 liteeth/phy: typo (thanks sb) 2015-03-12 21:54:10 +01:00
Florent Kermarrec cd6c04b24f soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx 2015-03-12 17:12:56 +01:00
Florent Kermarrec 767d45727a uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty). 2015-03-12 16:57:38 +01:00
Florent Kermarrec b157031e8a uart/sim: add pty (optional, to use flterm) 2015-03-09 23:29:06 +01:00
Florent Kermarrec 6cbf13036b liteeth/mac: fix padding limit (+1), netboot OK with sim platform 2015-03-09 20:59:34 +01:00
Florent Kermarrec 47cceea222 liteeth/mac: use Counter in sram and move some logic outside of fsms 2015-03-09 20:22:14 +01:00
Florent Kermarrec b10836a8eb liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit 2015-03-09 17:21:29 +01:00
Florent Kermarrec 1b58813d13 soc: do_exit is now provided by modules 2015-03-09 17:18:42 +01:00
Florent Kermarrec 360c849f21 liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter) 2015-03-09 13:23:39 +01:00
Florent Kermarrec 5dbd8af4be liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap 2015-03-09 13:23:37 +01:00
Florent Kermarrec d20b9c2221 uart: pass *args, **kwargs to sim phy 2015-03-06 12:08:10 +01:00
Florent Kermarrec af66ca7bad uart: add phy autodetect function 2015-03-06 10:19:29 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec bee8ccf6c7 soc: enforce cpu_reset_address to 0 when with_rom is True 2015-03-06 08:21:16 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Sebastien Bourdeauducq 60e87f6e87 Merge branch 'master' of https://github.com/m-labs/misoc 2015-03-04 00:46:41 +00:00
Sebastien Bourdeauducq 073641faa1 litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
Florent Kermarrec 200791c81d uart: generate ack for rx (serialboot OK with sim) 2015-03-04 00:57:37 +01:00
Florent Kermarrec 7c058a52c9 com/spi: use .format in tb 2015-03-03 10:44:05 +01:00
Florent Kermarrec 1d4dc45436 LiteXXX cores: use format in prints 2015-03-03 10:29:28 +01:00
Florent Kermarrec f27e7a4b22 litesata: remove unneeded clock constraint 2015-03-03 10:24:05 +01:00
Florent Kermarrec 0bcd6daf63 soc: remove is_sim function 2015-03-03 10:15:11 +01:00
Florent Kermarrec 905be50451 sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy 2015-03-03 09:55:25 +01:00
Florent Kermarrec 9210272356 sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence 2015-03-03 09:23:21 +01:00
Florent Kermarrec 2f7206b386 sdram: revert use of scalar values for DFIInjector 2015-03-03 09:09:54 +01:00
Florent Kermarrec 9df60bf98e lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True) 2015-03-03 09:02:53 +01:00
Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
Sebastien Bourdeauducq 8e48502d03 spiflash: style 2015-03-03 00:54:30 +00:00
Florent Kermarrec 410a162841 sdram: disable by default bandwidth_measurement on lasmicon 2015-03-02 19:53:16 +01:00
Florent Kermarrec 473997df26 cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
Florent Kermarrec 8280acd3a7 sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core 2015-03-02 12:17:49 +01:00
Florent Kermarrec 3465db25a7 soc/sdram: be more generic in naming 2015-03-02 11:55:28 +01:00
Florent Kermarrec 97331153e0 sdram: create core dir and move lasmicon/minicon in it 2015-03-02 11:38:22 +01:00
Florent Kermarrec de698c51e4 sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) 2015-03-02 11:29:43 +01:00
Florent Kermarrec 6b24562eea sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
Florent Kermarrec 46020fd253 sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look) 2015-03-02 10:34:29 +01:00
Florent Kermarrec c0b38e4905 sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus 2015-03-02 09:18:32 +01:00
Florent Kermarrec 7300879b7f sdram: move dfii to phy 2015-03-02 09:08:28 +01:00