Gwenhael Goavec-Merou
49488e5e01
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP i2c interface in EMIO mode
2024-05-17 11:02:31 +02:00
Gwenhael Goavec-Merou
e95edaf9be
soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP ethernet interface in EMIO mode (with gmii_to_rgmii)
2024-05-17 11:02:16 +02:00
Gwenhael Goavec-Merou
1986b79b9a
soc/cores/cpu/zynqmp/core.py: add_axi_gp_master: removed loop over layout to have a more clear / easy to maintain connexion
2024-05-17 11:02:02 +02:00
Gwenhael Goavec-Merou
c5592ca8da
soc/cores/cpu/zynqmp/core.py: allows user to specify default configuration (preset) with a tcl file
2024-05-17 11:01:46 +02:00
Dolu1990
0720ffb404
Update vexii
2024-05-17 10:00:24 +02:00
enjoy-digital
882463d9db
Merge pull request #1955 from Dolu1990/nax64_irq
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cores/cpu/naxriscv: fix 64 bits IRQ support
2024-05-17 08:20:46 +02:00
Dolu1990
122e060a5e
update vexii
2024-05-16 19:30:15 +02:00
Dolu1990
74b300597b
cpu/naxriscv: fix 64 bits IRQ support
2024-05-16 18:59:40 +02:00
Dolu1990
60b0273eda
Add baremetal IRQ support
2024-05-16 18:58:16 +02:00
Dolu1990
57f74da8d8
Merge branch 'master' into vexiiriscv
2024-05-16 16:17:21 +02:00
enjoy-digital
d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs
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Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
2024-05-16 10:55:12 +02:00
Florent Kermarrec
fbf03ec74c
inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it.
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Also cleanup self.mem.get_port call.
2024-05-16 10:36:44 +02:00
Florent Kermarrec
c0d9224f09
integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled.
2024-05-16 09:19:18 +02:00
Dolu1990
d4c1a10817
cores/cpu/naxriscv: Add baremetal IRQ support
2024-05-14 14:57:29 +02:00
Florent Kermarrec
e03b097e8e
software/libbase/isr.c: Simplify using __riscv_plic__ define.
2024-05-14 14:47:01 +02:00
Florent Kermarrec
c79e1ef95f
cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag.
2024-05-14 14:43:57 +02:00
Dolu1990
786c929f08
cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE
2024-05-14 14:24:37 +02:00
enjoy-digital
8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework
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Simplify/Cleanup C exports and disable Fields accessors generation by default.
2024-05-14 12:54:48 +02:00
Florent Kermarrec
8eaa53ae9a
test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).
2024-05-14 12:53:09 +02:00
enjoy-digital
c810b89464
Merge pull request #1951 from nuntipat/update-cv32e40p
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Update CV32E40P to be based on the OpenHW Group's repo
2024-05-14 12:11:50 +02:00
enjoy-digital
9b6e231a1a
Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p
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Fix CSR register definition for the CV32E41P core
2024-05-14 12:08:42 +02:00
Florent Kermarrec
46911d5078
soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects).
2024-05-14 11:59:13 +02:00
Florent Kermarrec
2574cc1ddc
integration/export: Fix read_function refactoring.
2024-05-14 11:55:34 +02:00
Dolu1990
7b7334fc17
cpu/vexiiriscv update
2024-05-14 11:41:21 +02:00
Florent Kermarrec
29bb397bb6
soc/integration/export: Add parameter to enable/disable fields access function generation.
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Fields access function have been contributed and probably used by a few project but not really
by LiteX projects or cores itselves.
This generates complex code and compilation warnings, so it can be useful to disable them by default (but still allow used to enable them).
2024-05-14 11:22:46 +02:00
Florent Kermarrec
9f4bd5cec8
integration/export: Split get_csr_header in simpler functions.
2024-05-14 11:00:41 +02:00
Florent Kermarrec
c42cc350c6
integration/export: Split _get_rw_functions_c in simpler functions.
2024-05-14 10:47:38 +02:00
Florent Kermarrec
3506a5e82d
cores/cpu/vexriscv_smp: Prepare IRQ support based on Rocket IRQ support (not yet working).
2024-05-14 10:04:13 +02:00
Florent Kermarrec
49897ee018
software/libbase/isr.c: Cleanup plic_init/isr and move PLIC_EXT_IRQ_BASE to cores/cpu/../irq.h since specific to each CPU.
2024-05-14 10:02:56 +02:00
Nuntipat Narkthong
b0acf6136e
Fix CSR register definition for the CV32E41P core
2024-05-13 20:03:16 -04:00
Nuntipat Narkthong
41564cc47b
Update CV32E40P to be based on the OpenHW Group's repo
2024-05-13 19:59:42 -04:00
Florent Kermarrec
2613ae606a
interconnect/packet/Status: Simplify logic.
2024-05-13 17:52:24 +02:00
Florent Kermarrec
8b175c2575
CHANGES: Update.
2024-05-13 16:33:11 +02:00
enjoy-digital
0d3a8220dd
Merge pull request #1948 from Liamolucko/riscv-triples
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Add missing 32-bit variants of RISC-V target triples
2024-05-07 15:15:09 +02:00
enjoy-digital
b61e8b5d42
Merge pull request #1945 from Nicolas-Gaudin/master
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Support isr for cv32e41p core
2024-05-07 15:13:44 +02:00
enjoy-digital
e4cfe87109
Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert
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Revert LitexModule for AXILiteSRAM as well.
2024-05-07 15:10:55 +02:00
Alexey Morozov
903c5fb9a1
handle the case when AWVALID and WVALID are not asserted at the same clock cycle
2024-05-07 13:33:04 +02:00
Dolu1990
588b7a9519
Update Vexii
2024-05-06 19:48:56 +02:00
Florent Kermarrec
86a43c9ff7
integration/export: Fix get_csr_header/base_define when with_csr_base_define is set to False.
2024-05-06 14:59:17 +02:00
Liam Murphy
e07c4fdb2a
Add missing 32-bit variants of RISC-V target triples
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I had to waste another 10-15 minutes building a `riscv64-none-elf` GCC
instead after LiteX didn't like my `riscv32-none-elf` one, so I thought
I'd quickly add it. (I was using that target triple because it's what
Nix's `pkgsCross.riscv32-embedded` package set uses).
I also added 32-bit variants of the rest of the target triples which
didn't have them.
2024-05-04 17:41:32 +10:00
Dmitry Derevyanko
26f5e8a149
Revert LitexModule for AXILiteSRAM as well. Follows revert d021564fca for wishbobe.
2024-05-03 00:51:01 +03:00
Nicolas Gaudin
bd0adb5be7
Support isr for cv32e41p core
2024-04-30 14:07:07 +02:00
enjoy-digital
76a704377f
Merge pull request #1941 from motec-research/vexriscv_debug_halted
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cpu/vexriscv: expose o_halted
2024-04-26 13:43:40 +02:00
Dolu1990
7aae2bf897
Merge pull request #1940 from enjoy-digital/Dolu1990-patch-1
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cpu/naxriscv update mBus to preserve memory accesses offset
2024-04-26 11:21:18 +02:00
Florent Kermarrec
fd477703db
soc/integration/export: Revert #1938 (needs to be reviewed/discussed).
2024-04-26 10:59:02 +02:00
AndrewD
bd4ca4371d
Merge pull request #1938 from motec-research/guard_access_function
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soc/export: add guard for access_functions
2024-04-26 12:06:49 +10:00
Andrew Dennison
3a008b4988
cpu/vexriscv: expose o_halted
2024-04-26 11:17:41 +10:00
Dolu1990
ea33e37b1a
cpu/naxriscv update mBus to preserve memory accesses offset
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See #1922
2024-04-25 16:06:34 +02:00
Dolu1990
8831acba65
naxriscv fix simulation reset
2024-04-25 16:01:49 +02:00
enjoy-digital
b6bfe42b6b
Merge pull request #1937 from motec-research/litex_term_deprecation_warning
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tools/litex_term: fix DeprecationWarning
2024-04-25 11:38:09 +02:00
