Sebastien Bourdeauducq
|
ccbd5e8baf
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framebuffer: chop memory words
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2012-06-29 16:11:05 +02:00 |
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Sebastien Bourdeauducq
|
0f9e16a034
|
framebuffer: ala flow->actorlib
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2012-06-24 19:15:19 +02:00 |
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Sebastien Bourdeauducq
|
53fec3191c
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framebuffer: control.For -> misc.IntSequence
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2012-06-22 15:01:25 +02:00 |
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Sebastien Bourdeauducq
|
ef13dc1eb1
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framebuffer: address generator and DMA
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2012-06-17 18:36:23 +02:00 |
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Sebastien Bourdeauducq
|
a52c3135c1
|
framebuffer: frame initiator
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2012-06-17 17:22:02 +02:00 |
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Sebastien Bourdeauducq
|
3a02524cc7
|
VGA framebuffer connections
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2012-06-17 13:41:26 +02:00 |
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Sebastien Bourdeauducq
|
f6f42293d1
|
Clock frequency detection
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2012-05-22 13:23:44 +02:00 |
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Sebastien Bourdeauducq
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5917048a37
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minimac: add tx start register
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2012-05-21 22:56:41 +02:00 |
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Sebastien Bourdeauducq
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94245517f2
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Add timer
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2012-05-21 19:46:04 +02:00 |
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Sebastien Bourdeauducq
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4e18e45686
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Add Ethernet MAC
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2012-05-20 00:30:03 +02:00 |
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Sebastien Bourdeauducq
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79124d822b
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Identifier
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2012-05-17 01:41:41 +02:00 |
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Sebastien Bourdeauducq
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425c8b8e70
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asmicon/multiplexer: fix read tag delay
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2012-05-15 13:13:40 +02:00 |
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Sebastien Bourdeauducq
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19b1cc2529
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Remove uses of pads, new constraints system
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2012-04-02 19:22:17 +02:00 |
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Sebastien Bourdeauducq
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d2c4afe66c
|
asmicon: various fixes. Now produces convincing refresh/read sequences.
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2012-04-01 23:24:24 +02:00 |
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Sebastien Bourdeauducq
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ac7d89a4fe
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asmicon/bankmachine: fixes
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2012-03-31 09:55:52 +02:00 |
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Sebastien Bourdeauducq
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cd82f16806
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asmicon/refresher: fix refresh sequence done signal
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2012-03-30 16:26:50 +02:00 |
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Sebastien Bourdeauducq
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c26efa28ca
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asmicon: multiplexer (untested)
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2012-03-18 22:11:01 +01:00 |
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Sebastien Bourdeauducq
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0e00837f42
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asmicon: move slot time to timing settings
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2012-03-18 14:57:31 +01:00 |
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Sebastien Bourdeauducq
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b1eb919ad2
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asmicon: bank machine (untested)
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2012-03-18 00:12:03 +01:00 |
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Sebastien Bourdeauducq
|
7c377880fa
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asmicon: refresher (untested)
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2012-03-15 20:29:26 +01:00 |
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Sebastien Bourdeauducq
|
e3ef121440
|
norflash: use new timeline API
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2012-03-15 20:26:04 +01:00 |
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Sebastien Bourdeauducq
|
7b14e0bd05
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asmicon: skeleton
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2012-03-14 18:26:05 +01:00 |
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Sebastien Bourdeauducq
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baba267db6
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ddrphy: request wrdata_en/rddata_en at the same time as the command
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2012-02-24 15:14:58 +01:00 |
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Sebastien Bourdeauducq
|
3179a27d14
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dfii: set data mask
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2012-02-23 22:00:51 +01:00 |
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Sebastien Bourdeauducq
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92ac69bae3
|
dfii: new design
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2012-02-23 21:21:07 +01:00 |
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Sebastien Bourdeauducq
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b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
|
f35cd4a85b
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Prepare for new DDR PHY
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2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
|
026457a98c
|
Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
|
2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
|
5bc840b9c1
|
DFI injector (untested)
|
2012-02-17 23:50:10 +01:00 |
|
Sebastien Bourdeauducq
|
c387ce7ce5
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Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
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Sebastien Bourdeauducq
|
5d1dad583b
|
Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |
|
Sebastien Bourdeauducq
|
cc5e4ae710
|
clkfx: remove
|
2012-02-16 19:30:00 +01:00 |
|
Sebastien Bourdeauducq
|
204452b0d3
|
m1crg: make clock feedback pin bidirectional
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2012-02-16 18:35:44 +01:00 |
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Sebastien Bourdeauducq
|
f36a45edcb
|
lm32: compatibility with the new instance API
|
2012-02-16 18:35:22 +01:00 |
|
Sebastien Bourdeauducq
|
72f9af9d90
|
Generate all clocks for the DDR PHY
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2012-02-16 18:02:37 +01:00 |
|
Sebastien Bourdeauducq
|
859c9d8849
|
Use new bus API
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2012-02-15 16:55:13 +01:00 |
|
Sebastien Bourdeauducq
|
506ffab11a
|
uart: RX support
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2012-02-07 14:12:23 +01:00 |
|
Sebastien Bourdeauducq
|
58f4f78d2c
|
sram: fix sub-word write
|
2012-02-06 23:13:35 +01:00 |
|
Sebastien Bourdeauducq
|
5dc875de69
|
UART: use new bank API and event manager
|
2012-02-06 17:45:31 +01:00 |
|
Sebastien Bourdeauducq
|
b5cb1083ab
|
sram: fix WE signal
|
2012-02-03 10:38:17 +01:00 |
|
Sebastien Bourdeauducq
|
8a2646a549
|
Remove explicit bus names
|
2012-01-27 22:21:08 +01:00 |
|
Sebastien Bourdeauducq
|
28f00c3a9a
|
Add on-chip SRAM
|
2012-01-27 22:09:03 +01:00 |
|
Sebastien Bourdeauducq
|
6fde54c5aa
|
Use meaningful class names
|
2012-01-21 12:25:22 +01:00 |
|
Sebastien Bourdeauducq
|
f8d5c27ef8
|
Wishbone: omit fixed LSBs
|
2012-01-13 17:28:58 +01:00 |
|
Sebastien Bourdeauducq
|
b60abfaa4a
|
Convert -> convert
|
2012-01-05 19:27:45 +01:00 |
|
Sebastien Bourdeauducq
|
3b640c45bb
|
Use new syntax
|
2011-12-18 22:02:05 +01:00 |
|
Sebastien Bourdeauducq
|
6664af73d1
|
uart: new design using FHDL and bank (TX only, incomplete)
|
2011-12-18 00:29:37 +01:00 |
|
Sebastien Bourdeauducq
|
bb21f7584a
|
32-device, 8-bit CSR bus
|
2011-12-17 15:54:42 +01:00 |
|
Sebastien Bourdeauducq
|
85fbe07b94
|
clkfx module
|
2011-12-17 15:00:11 +01:00 |
|
Sebastien Bourdeauducq
|
411e1af980
|
Proper reset generation
|
2011-12-16 22:25:26 +01:00 |