enjoy-digital
cd1088dbe9
Merge pull request #1884 from motec-research/efinix_spi_width
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Efinix: suport spi width for passive loading
2024-02-05 12:43:30 +01:00
Andrew Dennison
f81c940e7b
litex/build/efinix: add binary output
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This is the file required for passive SPI loading.
2024-02-05 11:00:39 +11:00
Andrew Dennison
d9f006e123
litex/build/efinix: add spi_width
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Doesn't seem needed for Trion but probably essential for Titanium?
2024-02-05 11:00:39 +11:00
Florent Kermarrec
a59b67e4ee
soc: Avoid .upper() on add_config/constant since already done in methods.
2024-02-01 08:44:52 +01:00
Florent Kermarrec
e498a56698
soc/add_spi_flash: Minor integration cleanup and remove PHY_FREQUENCY constants that is no longer used.
2024-02-01 08:42:11 +01:00
Florent Kermarrec
e44631294a
CHANGES.md: Update.
2024-02-01 08:34:17 +01:00
enjoy-digital
be23467cb1
Merge pull request #1881 from motec-research/spiflash_fixes
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Spiflash fixes for issues exposed by sys_clk = 200MHz and L2 cache
2024-02-01 08:33:36 +01:00
Andrew Dennison
fc85fdd178
build/openfpgaloader: support args with '-'
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many openfpgaloader args have a name with '-' as per normal convention.
This kwarg now works: file_type="raw"
2024-02-01 15:53:51 +11:00
Andrew Dennison
afe7b93995
software/liblitespi/spiflash: fix warnings
2024-02-01 14:37:22 +11:00
Andrew Dennison
de594e44c9
software/bios/cmds: fix crc command with L2 cache
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Same CRC was always reported if the memory region was in the cache...
Noticed when manually testing spiflash divisor.
2024-02-01 14:37:22 +11:00
Andrew Dennison
3a890a077b
software/liblitespi/spiflash: fix clk_freq tuning with L2 cache
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Correct CRC was always calculated, regardless of divisor, as the
test flash block was in the L2 cache. This resulted in the minimum
divisor being used and incorrect flash reads with 200MHz sys_clock.
2024-02-01 14:37:22 +11:00
Andrew Dennison
e0416639f7
software/liblitespi/spiflash: fix reported flash clk
2024-02-01 14:37:22 +11:00
Andrew Dennison
51c3cb3552
soc/add_spi_flash: default clk_freq to 20MHz
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This is safer than defaulting to sys_clock / 2 if sys_clock > 100MHz
clk_freq tuning will result in a faster clock if supported by hardware.
2024-02-01 14:37:22 +11:00
Andrew Dennison
1dddfa6841
soc/add_spi_flash: fix default divisor and PHY_CLOCK calculation
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Ensure default_divisor is set to desired default - 1 as required by LiteSPIClkGen
Calculate actual PHY_CLK based on default_divisor
2024-02-01 14:37:22 +11:00
Andrew Dennison
08189663ba
soc/add_spi_flash: fix bios 1x mode support
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require both phy and flash support to enable QUAD/QPI capability.
Many flash devices support 4x read but may be on a 1x phy
2024-02-01 14:37:22 +11:00
Andrew Dennison
4dae3a9f4d
build/openfpgaloader: report command line on error
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Helps explain failures
2024-02-01 14:37:16 +11:00
Florent Kermarrec
f73fbee309
cores/spi/spi_master: Improve documentation, especially on Raw/Aligned mode and CS control.
2024-01-30 10:57:09 +01:00
Florent Kermarrec
a3904ac26d
CHANGES.md: Update.
2024-01-30 09:51:05 +01:00
Florent Kermarrec
488247e4f7
build/efinix/programmer: Define EFXDBG_HOME now required by latest Efinity versions.
2024-01-30 09:44:52 +01:00
Gwenhael Goavec-Merou
245bed7195
soc/cores/clock/efinix: fix input clock code for trion when the input clock comes from another PLL
2024-01-25 17:39:12 +01:00
Gwenhael Goavec-Merou
d32095540a
soc/integration/soc: add_ethernet/add_ip_constants: cast str to int (avoid double quote in soc.h
2024-01-24 16:06:44 +01:00
Florent Kermarrec
f543b18d02
soc/add_ethernet: Refactor local/remote_ip configuration and add basic checks for IP address length + validity.
2024-01-24 15:28:18 +01:00
enjoy-digital
115e87ff4f
Merge pull request #1877 from trabucayre/ethernet_local_remote_ip
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soc/integration/soc: add_etherbone: allowing to specify local/remote IP
2024-01-24 15:15:31 +01:00
Gwenhael Goavec-Merou
bcde71b051
soc/integration/soc: add_etherbone: allowing to specify local/remote IP
2024-01-24 15:13:42 +01:00
enjoy-digital
1be3f0297d
Merge pull request #1876 from trabucayre/vexriscv_configurable_clint_csr_addr
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soc/cores/cpu/vexriscv_smp/core: allowing configure CSR/CLINT base address by overriding default value or using args
2024-01-23 16:27:16 +01:00
Florent Kermarrec
c31ec79981
CHANGES.md: Update.
2024-01-23 16:02:11 +01:00
Gwenhael Goavec-Merou
bb62f7aa63
soc/cores/cpu/vexriscv_smp/core: allowing configure CSR/CLINT/PLIC base address by overriding default value or using args
2024-01-22 18:36:51 +01:00
enjoy-digital
4c07d72af3
Merge pull request #1874 from trabucayre/naxriscv_arch
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soc/cores/cpu/naxriscv fix arch definition and small adjust
2024-01-19 10:22:43 +01:00
Gwenhael Goavec-Merou
854541d5c7
soc/cores/cpu/naxriscv/core: adding argument to enable rvc extension
2024-01-19 07:37:55 +01:00
Gwenhael Goavec-Merou
f00d49211b
soc/cores/cpu/naxriscv/core: force go back previous directory after git clone
2024-01-18 15:21:37 +01:00
Gwenhael Goavec-Merou
4222a585c9
soc/cores/cpu/naxriscv/core: fix arch definition
2024-01-18 15:04:09 +01:00
Florent Kermarrec
b19d992f23
inteconnect/ahb: Add specific case for 32-bit data width, fix CSR accesses with gowin_ae350.
2024-01-15 11:40:25 +01:00
Florent Kermarrec
6b79644108
cores/cpu/gowin_emcu: Switch to LiteX's UART.
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A UART does not cost that much ressources and this avoid specific code/allow simplifying support.
2024-01-11 13:53:15 +01:00
Florent Kermarrec
8aa5958fb7
cores/cpu: Add intitial gowin_ae350 support.
2024-01-11 13:11:56 +01:00
Florent Kermarrec
e689aab18a
interconnect/ahb/AHB2Wishbone: Add proper Wishbone sel decoder/support.
2024-01-11 10:17:22 +01:00
Florent Kermarrec
80dfb5ca34
interconnect/ahb/AHB2Wishbone: Simplify and add proper Address/Data-Phases.
2024-01-10 12:10:15 +01:00
Gwenhael Goavec-Merou
a2c2d70841
build/gowin/gowin: adding list of additional cst commands (to place resources)
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
2024-01-10 10:30:41 +01:00
Gwenhael Goavec-Merou
31d3325219
build/gowin/platform: adding mock add_false_path_constraint method
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
2024-01-10 10:30:36 +01:00
Gwenhael Goavec-Merou
91fbc79ac2
build/gowin/common: adding missing TX/Q1 ODDR signals
2024-01-08 07:28:56 +01:00
Florent Kermarrec
718c26d8fc
cpu/gowin_emcu: Add interfaces directly to instances and simplify/cleanup to remove some warnings.
2024-01-04 19:33:43 +01:00
Florent Kermarrec
c61d2de13b
CHANGES.md: Update.
2024-01-04 15:37:58 +01:00
Florent Kermarrec
cf165d3c2c
README/Bios: Bump year.
2024-01-04 15:33:01 +01:00
Florent Kermarrec
739a8db8c3
cpu/gowin_emcu: Specify AHB data_width/address_width.
2024-01-04 15:30:47 +01:00
Florent Kermarrec
7009299132
interconnect/ahb: Simplify AHBInterface and add data_width/address_width parameters.
2024-01-04 15:30:26 +01:00
Florent Kermarrec
02f0a96c84
interconnect/ahb: Add AHB prefix to TransferType/Interface (similar to AXI).
2024-01-04 15:21:32 +01:00
Florent Kermarrec
55e2a1cec6
cpu/gowin_emcu: Switch pbus to byte addresssing.
2024-01-04 13:13:21 +01:00
Florent Kermarrec
5bbcda4d5c
interconnect/ahb/AHB2Wishbone: Fix size check that is too restrictive, can be <= log2_int(ahb.data_width//8).
2024-01-04 13:12:29 +01:00
Florent Kermarrec
6a6837062a
cpu/gowin_emcu: Remove interrupt signal since not yet functional/used.
2024-01-04 10:40:47 +01:00
Florent Kermarrec
386854cbd3
cpu/gowin_emcu: Use crt0.c from cortex_m3.
2024-01-04 10:38:45 +01:00
Florent Kermarrec
de6fbf1271
cpu/gowin_emcu: Directly connect AHB interfaces, using for loops make things unclear/difficult to follow.
2024-01-04 10:33:50 +01:00
