c98bd9fd79
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
2015-05-02 17:07:58 +02:00
63b8797978
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
93de581931
soc: add shadow_address parameter
...
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
2015-04-17 13:42:29 +02:00
2ccb5655c9
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 18:02:26 +02:00
fc68d915c1
global: pep8 (E261, E271)
2015-04-13 17:16:12 +02:00
f68423f423
global: pep8 (E302)
2015-04-13 16:47:22 +02:00
d9e09707ae
global: pep8 (replace tabs with spaces)
2015-04-13 16:19:55 +02:00
369086a178
soc: simplify integrated memory parameters
2015-04-02 00:09:38 +08:00
c55199deb9
misoclib/soc: add _integrated_ to cpu options to avoid confusion
2015-03-21 20:51:37 +01:00
b2f32ad124
targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains)
2015-03-17 01:07:44 +01:00
28d04ec300
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
2015-03-14 00:49:19 +01:00
d09529d483
targets/simple: use mibuild default clock
2015-03-14 00:11:59 +01:00
1b72b81f9c
targets/simple: use new generic DifferentialInput
2015-03-12 18:36:04 +01:00
f18ae9b9fe
targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors)
2015-03-12 17:25:01 +01:00
e133777450
targets/simple: add MiniSoC
2015-03-06 10:10:58 +01:00
b32a0e6f9e
liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
2015-02-28 23:33:00 +01:00
69e869893d
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
07b9cabd0d
gensoc: make it more generic (a SoC does not necessarily have a CPU)
2015-02-27 16:39:00 +01:00
5e8a0c496d
gensoc: add mem_map and mem_decoder to avoid duplications
2015-02-26 20:12:27 +01:00
554731ae44
targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
2015-02-26 13:08:15 +01:00
13fb9282db
targets: add simple design (vendor agnostic and usable on all platforms with UART pins).
...
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
2014-09-26 10:35:15 +08:00
213cb43ae5
Keep only basic SoC designs in MiSoC
2014-08-03 12:30:15 +08:00
ac97815619
targets/simple: pass kwargs
2014-05-24 11:29:03 +02:00
e9b49ebb44
Use SDRAM on the Papilio Pro
...
Based on code by Robert Jordens
2014-05-23 21:26:09 +02:00
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
41c35e7e0c
simple: create PowerOnRst and use it (remove vendor-dependent code)
2014-04-17 19:39:05 +02:00
362f938736
simplesoc: free LED
2014-04-14 00:23:41 +02:00
0c3f8f703d
targets/simple: add dummy SDRAM + flash boot address
2014-04-08 15:25:49 +02:00
fce46ac0ca
Simplify use of external targets/platforms/cores + add default platform in targets
2014-02-16 14:51:52 +01:00
e4273be517
targets/simple: use XIP from SPI flash
2014-02-14 15:48:15 +01:00
ad974a07ef
gensoc: support for user-defined UART and add default values for SRAM and L2 sizes
2014-01-06 22:12:42 +01:00
356178e680
targets/simple: map SPI flash
2013-11-25 15:08:53 +01:00
b49e6f07b2
targets/simple: add GPIO LED
2013-11-25 12:16:20 +01:00
78cd7a288e
move integrated BIOS code to gensoc
2013-11-25 10:22:14 +01:00
0dfaf6876a
targets: add simple SoC
2013-11-24 23:52:05 +01:00
Florent Kermarrec
Sebastien Bourdeauducq
Sebastien Bourdeauducq