d03dabb460
common.mak: Pass -fexceptions to clang and clang++.
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This results in generation of .eh_frame sections. These sections
can be discarded during final linking, or included if exception
handling is desired. For exception handling to work, all sources
must be built with -fexceptions.
2015-07-26 03:30:21 +03:00
69c2a705bf
common.mak: use clang/clang++ to compile C/C++ sources.
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Note that -integrated-as is not active by default on OR1K,
so we're still shelling out to binutils to assemble.
It is not yet possible to build everything using -integrated-as.
2015-07-26 03:28:37 +03:00
0f47876d2e
common.mak: remove RANLIB.
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`ranlib` is not necessary on any system we can possibly build for,
as it is superseded by `ar s` for the last ten years or so (at least).
Thus, change ar invocations to `ar crs`, also removing a `l` flag
that is ignored by binutils.
2015-07-26 03:20:23 +03:00
f500b906e6
common.mak: remove AS.
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$(AS) was never used: $(assemble) invokes the C compiler instead.
In case of LLVM, this will allow us to consistently use the LLVM
internal assembler for both inline assembly in C and assembly
sources; so, avoid ever invoking binutils as explicitly.
2015-07-26 02:46:03 +03:00
8d1c555e36
misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.
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An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.
2015-07-25 00:25:09 +02:00
ce11b30140
misoclib: integrate mxcrg.py in mlabs_video target, remove others directory
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we should also get rid of mxcrg.v (similar to what is done on papilio or pipstrello)
2015-07-24 23:16:45 +02:00
b75b93df43
misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
2015-07-24 14:05:54 +02:00
0a115f609e
litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)
2015-07-24 13:52:57 +02:00
d73d75007e
misoclib/com/uart: cleanup and add irq condition parameters
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- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
2015-07-24 12:57:42 +02:00
b1ea3340f3
litepcie/frontend/dma: add loop counter (useful to detect missed interrupts)
2015-07-22 22:55:11 +02:00
dfc207aacb
litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)
2015-07-22 21:44:53 +02:00
40740d3ddc
litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
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We should eventually try to use python package_data or data_file for that.
2015-07-22 18:09:04 +02:00
84514cf8d5
uart: remove option to refill HW from uart_write
2015-07-19 23:41:38 +02:00
a501d7c52d
uart: support async phys
2015-07-19 23:37:00 +02:00
097248bce9
uart.c: rx overflow fix and tx simplification
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* fixes the clearing of the rx ringbuffer on rx-overflow
* removes tx_level and tx_cts by restricting the ringbuffer
to at least one slot empty
* agnostic of the details of the tx irq: works for uarts that
generate tx interrupts on !tx-full or on tx-empty.
* only rx_produce and tx_consume need to be volatile
2015-07-19 23:37:00 +02:00
35250f5b11
bios: add romboot
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When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.
2015-07-14 18:01:44 +02:00
6c13879fb6
make.py: use sys.path.insert(0...) to allow external designs to have specific targets derived from a base target
2015-07-13 17:25:50 +02:00
4dca66b23d
misoclib/video/dvisampler: add fifo_depth parameter
2015-07-13 11:03:33 +02:00
e6da1d16b2
wishbone2lasmi: fix "READ_DATA" state
2015-07-09 10:40:32 +02:00
d244eba583
tools/flterm.py: fix kernel-adr support
2015-07-07 14:58:49 +02:00
0545d49294
liteeth/core: add with_icmp parameter
2015-07-06 21:31:20 +02:00
e011f9378f
use sets for leave_out
2015-07-05 22:49:23 +02:00
c100ef6406
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)
2015-07-05 22:45:53 +02:00
c1ca928ec2
liteeth: small logic optimizations on mac (eases timings on spartan6)
2015-07-05 12:31:52 +02:00
23541b5949
software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)
2015-07-04 21:04:23 +02:00
10eb07526d
bios: show memtest command in help
2015-07-02 17:20:06 +02:00
31a447154d
soc: support constants without value
2015-06-28 21:35:37 +02:00
e913fca8a0
libcompiler-rt: add fixdfdi
2015-06-27 23:51:09 +02:00
a1e3fb16ac
flterm.py: use serial_for_url
2015-06-26 11:40:33 +02:00
04c64eb1d8
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00
c615b50735
Merge pull request #14 from olofk/misc_fixes
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Misc fixes
2015-06-25 23:59:42 +02:00
52e6bf6987
litesata/test: Add missing dependency on scrambler in bist_tb
2015-06-26 01:20:25 +02:00
ffb6081720
litesata/example_designs: Add missing clock in phy instantiation
2015-06-26 01:20:25 +02:00
125432b5b6
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
351e654e9d
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
2015-06-23 09:01:34 +02:00
2150e6cfef
pipistrello: run at 83+1/3 MHz, cleanup CRG
2015-06-22 18:56:57 -06:00
01c5051866
liteeth/software: fix wishbone bridge
2015-06-23 01:48:45 +02:00
369cf4c4d7
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
2015-06-23 01:08:49 +02:00
5c939b85ef
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
2015-06-23 00:25:26 +02:00
a3c0e5c4d9
liteeth/core/arp: fix missing MAC address in ARP reply
2015-06-22 23:15:00 +02:00
781869d6f9
software/libbase/system: fix flush_l2_cache
2015-06-19 09:00:14 +02:00
f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
7c2d0fa641
indentation
2015-06-17 08:32:17 -06:00
c0bc94ca1c
soc/sdram: add capability to share L2 cache in multi-CPU SoCs
2015-06-17 15:48:45 +02:00
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
a1f7ecc8c5
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
571ce5791a
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
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self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
1bb2580779
sdram: use new Migen Converter in Minicon frontend and small cleanup
2015-06-02 19:37:08 +02:00
f96a856c97
sdram/phy: fix simphy memory usage
2015-06-02 19:33:09 +02:00
f40140dba5
sdram: refactor minicon and fix issues with DDRx memories
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- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
whitequark
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens
Yann Sionneau
Joe Britton
Olof Kindgren