Florent Kermarrec
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4a59b63151
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Clean up
|
2012-09-09 23:46:26 +02:00 |
|
Florent Kermarrec
|
7a24ee7027
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Wip de0_nano example
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2012-09-09 23:27:51 +02:00 |
|
Florent Kermarrec
|
6b8dda03c6
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Wip de0_nano example
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2012-09-09 22:32:09 +02:00 |
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Florent Kermarrec
|
1578c74895
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Initialize de0_nano example
|
2012-09-09 21:18:09 +02:00 |
|
Florent Kermarrec
|
b8eaf0906a
|
Clean up
|
2012-09-09 20:51:15 +02:00 |
|
Florent Kermarrec
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2092c5a138
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add global tb, fix bugs
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2012-09-09 20:38:01 +02:00 |
Sebastien Bourdeauducq
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f40ca52e5f
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setup.py: cosmetic
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2012-09-09 19:56:04 +02:00 |
|
Sébastien Bourdeauducq
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6490785b6c
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Merge pull request #3 from brandonhamilton/upstream
Optionally accept iverilog simulator options
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2012-09-09 10:52:52 -07:00 |
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Sebastien Bourdeauducq
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2a7d2908d1
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examples: new namer
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2012-09-09 19:34:46 +02:00 |
|
Sebastien Bourdeauducq
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b45c9546eb
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fhdl/namer: better handling of indices
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2012-09-09 19:33:55 +02:00 |
|
Sebastien Bourdeauducq
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589251fffd
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fhdl/tracer: support BUILD_LIST opcode
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2012-09-09 18:53:24 +02:00 |
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Sebastien Bourdeauducq
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910c350021
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fhdl/namer: use execution order indices for variable names as well
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2012-09-09 17:31:35 +02:00 |
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Florent Kermarrec
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289d35b952
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simplify registers mgnt
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2012-09-09 14:37:55 +02:00 |
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Sebastien Bourdeauducq
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f3e3a3eec7
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fhdl/namer: number objects according to execution order
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2012-09-09 12:27:32 +02:00 |
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Sebastien Bourdeauducq
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51f9a2a963
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fhdl/namer: simplify + more relevant names
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2012-09-09 01:26:33 +02:00 |
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Florent Kermarrec
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2abd7f664d
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add tb_RecorderCsr.py
fixs in recorder.py
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2012-08-27 00:44:26 +02:00 |
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Florent Kermarrec
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d34c877401
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split migScope to trigger & recorder
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2012-08-26 21:30:23 +02:00 |
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Sebastien Bourdeauducq
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4164fb4ac9
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bus/csr: configurable data width
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2012-08-26 21:19:34 +02:00 |
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Florent Kermarrec
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a99a902fef
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add vcd generator
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2012-08-26 20:56:56 +02:00 |
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Florent Kermarrec
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97cca81e0c
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tb_TriggerCsr.py : use truth table generator for Sum Lut
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2012-08-26 15:44:43 +02:00 |
|
Florent Kermarrec
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68750445cd
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add truth table generator
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2012-08-26 15:15:44 +02:00 |
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Florent Kermarrec
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bf7864104a
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tb_spi2Csr: Add clk_ratio
tb_spi2Csr: Add Read
spi2Csr : fixs
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2012-08-26 13:03:11 +02:00 |
|
Florent Kermarrec
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2e54001fc1
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- fix Spi2Csr mistakes
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2012-08-25 23:29:23 +02:00 |
|
Florent Kermarrec
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b5a44f2e98
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add sim: tb_Spi2Csr.py (skeleton, WIP)
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2012-08-25 21:53:06 +02:00 |
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Florent Kermarrec
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d14ffb9146
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add sim: tb_TriggerCsr.py
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2012-08-25 18:46:58 +02:00 |
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Florent Kermarrec
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a7d85af25b
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use ram for Sum
|
2012-08-24 00:16:00 +02:00 |
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Florent Kermarrec
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f4cac2c102
|
Add simulation skeleton
Remove SRLC16E, will be replaced by distributed ram
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2012-08-22 23:59:00 +02:00 |
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Florent Kermarrec
|
7dd51b3d92
|
new library spi2Csr (skeleton)
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2012-08-13 01:02:38 +02:00 |
|
Florent Kermarrec
|
f586b13d4b
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add register interface to Trigger
|
2012-08-12 21:17:17 +02:00 |
|
Florent Kermarrec
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051e8ac570
|
simplify EdgeDetector
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2012-08-12 19:42:25 +02:00 |
|
Florent Kermarrec
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09bcfb0fa5
|
fix masks on EdgeDetector
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2012-08-12 19:39:26 +02:00 |
|
Florent Kermarrec
|
68c451148a
|
add Trigger
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2012-08-12 19:30:27 +02:00 |
|
Sebastien Bourdeauducq
|
9aa5ceb6d9
|
doc: ASMI reader
|
2012-08-12 18:04:29 +02:00 |
|
Sebastien Bourdeauducq
|
dc241639fd
|
doc: IntSequence
|
2012-08-12 17:55:29 +02:00 |
|
Florent Kermarrec
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449466d5b7
|
rename Recorder --> Storage
add Recorder
|
2012-08-12 17:31:15 +02:00 |
|
Florent Kermarrec
|
18452c8193
|
add simple Sequencer
|
2012-08-12 16:04:52 +02:00 |
|
Florent Kermarrec
|
d22101eaa1
|
add Readme
|
2012-08-12 14:41:17 +02:00 |
|
Florent Kermarrec
|
db2d3418c3
|
add Readme
|
2012-08-12 14:38:49 +02:00 |
|
Florent Kermarrec
|
dbb363f039
|
- init Repo
|
2012-08-12 14:21:30 +02:00 |
|
Sebastien Bourdeauducq
|
dad4a91793
|
doc: framebuffer example
|
2012-08-08 17:30:18 +02:00 |
|
Sebastien Bourdeauducq
|
166e03d5f0
|
doc: arrays
|
2012-08-06 19:12:33 +02:00 |
|
Sebastien Bourdeauducq
|
42d5e850fe
|
framebuffer: disable debugger by default
|
2012-08-05 01:11:37 +02:00 |
|
Sebastien Bourdeauducq
|
5bf19c155f
|
sim: ensure clean IPC shutdown
|
2012-08-05 00:16:11 +02:00 |
|
Sebastien Bourdeauducq
|
47c341ecdf
|
flow/isd: add freeze register
|
2012-08-04 23:39:52 +02:00 |
|
Sebastien Bourdeauducq
|
5ef8d5f534
|
bios/dataflow: use freeze register
|
2012-08-04 23:39:29 +02:00 |
|
Sebastien Bourdeauducq
|
a5d6ced181
|
asmicon: fix and simplify refresh grant logic
|
2012-08-04 22:59:21 +02:00 |
|
Sebastien Bourdeauducq
|
ea4c214790
|
asmicon/bankmachine: respect SDRAM write-to-precharge specification
|
2012-08-04 22:49:43 +02:00 |
|
Sebastien Bourdeauducq
|
1451cad710
|
asmicon/multiplexer: correct read-to-write delay to prevent conflicts on the tag bus
|
2012-08-04 17:38:42 +02:00 |
|
Sebastien Bourdeauducq
|
274a00217e
|
bios: asmiprobe command
Because with reordering architectures come order-dependent intermittent bugs.
|
2012-08-04 16:32:15 +02:00 |
|
Sebastien Bourdeauducq
|
855eec776d
|
Add ASMIprobe core
|
2012-08-04 16:31:24 +02:00 |