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4022 Commits

Author SHA1 Message Date
Florent Kermarrec c506c9752c gen/fhdl/verilog: set direction to io signals 2018-10-29 11:41:04 +01:00
Tim Ansell 9815920946
Merge pull request #120 from mithro/master 
litex/build: Always run Vivado.
 2018-10-29 02:08:20 -07:00
Tim 'mithro' Ansell 1cac079efa litex/build: Always run Vivado. 
When using Yosys for synthesis, still need Vivado for place and route.
 2018-10-29 02:04:44 -07:00
Florent Kermarrec 49dab3b448 build/lattice/prjtrellis: simplify code, remove some workarounds 2018-10-29 09:40:35 +01:00
Florent Kermarrec a73d9d96b1 build/xilinx/vivado: fix merge issue 2018-10-29 08:26:13 +01:00
Florent Kermarrec 3e189379f9 boards/targets: add versa ecp55g prjtrellis target (experimental) 2018-10-28 19:34:17 +01:00
Florent Kermarrec a69197d2db build/lattice: add initial prjtrellis support 2018-10-28 17:51:16 +01:00
Florent Kermarrec 397e3c7682 build/lattice/diamond: use bash on linux 2018-10-28 15:40:52 +01:00
Florent Kermarrec d029cd243d build/lattice: improve special_overrides names (vendor_family) 2018-10-28 15:40:10 +01:00
enjoy-digital 60665358d4
Merge pull request #114 from mithro/xilinx+yosys 
WIP: Allow Yosys to be used for synthesis with Vivado
 2018-10-28 15:00:06 +01:00
enjoy-digital b200ce9983
Merge branch 'master' into xilinx+yosys 2018-10-28 14:59:03 +01:00
enjoy-digital 8c0982a1d5
Merge pull request #118 from mithro/uart-sync 
uart: Enable buffering the FIFO.
 2018-10-28 08:02:22 +01:00
Tim 'mithro' Ansell ba0dd5728e uart: Enable buffering the FIFO. 
On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
 2018-10-27 16:04:58 -07:00
Florent Kermarrec f916705313 README: improve instructions for litex_sim 2018-10-27 11:06:53 +02:00
Florent Kermarrec e3935b481e build/sim/verilator: don't use THEADS parameters when threads=1 
Allow using old (non multi-threaded) version of Verilator
 2018-10-27 11:06:34 +02:00
Florent Kermarrec a44181e716 soc_sdram: update litedram 2018-10-19 18:37:55 +02:00
Florent Kermarrec ab6a530a24 bios/sdram: s7ddrphy now has bitslip in fabric, show scan for each module/bitslip and remove silent mode 2018-10-18 13:42:51 +02:00
Florent Kermarrec b8be9545cc build/xilinx/vivado: enable xpm libraries 2018-10-18 09:25:34 +02:00
Florent Kermarrec ab8cf3e345 soc/cores/clock: add margin parameter to create_clkout (default = 1%) 2018-10-16 14:57:37 +02:00
Florent Kermarrec 915c2f417a bios/sdram: improve write/read leveling 
write_leveling: select last 0 to 1 transition.
read_leveling: do it by module (select best bitslip for each module)
 2018-10-10 10:42:56 +02:00
Florent Kermarrec deffa60324 platforms/kc705: add ddram_dual_rank 2018-10-09 15:39:03 +02:00
Florent Kermarrec 10624c26da bios/main: handle all types of carriage return (\r, \n, \r\n or \n\r) 2018-10-09 10:06:51 +02:00
enjoy-digital 9f083e9bd3
Merge pull request #116 from stffrdhrn/sim-uart 
sim: serial: Send '\r\n' instead of just '\n'
 2018-10-09 07:32:31 +02:00
Stafford Horne 8877dba7e9 sim: serial: Send '\r\n' instead of just '\n' 
This fixes an issue when running with the HDMI2USB firmware which
expects \r\n to come from the UART.  Since the verilator adapter
is just sending \n commands cannot be executed.

Also, one minor whitespace cleanup. (could remove if needed)
 2018-10-09 11:18:11 +09:00
Florent Kermarrec d187921500 cpu_interface: fix select_triple when only one specified 2018-10-08 17:01:04 +02:00
Florent Kermarrec 3b27d2ae89 soc/integration/cpu_interface: generate error if unable to find any of the cross compilation toolchains 2018-10-06 21:32:38 +02:00
Florent Kermarrec 168b07b9a2 soc_core: add csr range check 2018-10-06 20:55:16 +02:00
Tim 'mithro' Ansell ace976242e build.xilinx: Convert attributes to something Yosys understands. 
Convert keep, dont_touch and async_reg to something Yosys understands.

Write out an EDIF file with the attributes so that Vivado can use them.
(Requires Yosys with commit
115ca57647)
 2018-10-05 12:48:30 -07:00
enjoy-digital 6febb6826c
Merge pull request #112 from cr1901/8k-b-evn 
build/platforms: Add ice40_hx8k_b_evn from Migen.
 2018-10-04 21:12:33 +02:00
enjoy-digital 9cf4ffb3f4
Merge pull request #113 from stffrdhrn/litex-trivial 
Litex trivial
 2018-10-04 16:25:11 +02:00
Stafford Horne ff6de429f0 Fix help for or1k builds 
The help said cpu-type could be mor1kx, which is correct but you must
pass or1k to get mor1kx.  Fix the message to properly represent what
needs to be passed to the commandline.
 2018-10-04 23:09:49 +09:00
Stafford Horne dafdb8df72 Fix compiler warnings from GCC 8.1 
Fix these 2 warnings:

 litex/build/sim/core/libdylib.c:42:5: warning: 'strncpy' specified bound 2048 equals destination size
 [-Wstringop-truncation]
     strncpy(last_err, s, ERR_MAX_SIZE);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 In function 'set_last_error',

 litex/soc/software/libbase/exception.c:28:13: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  static char emerg_getc()
 2018-10-04 23:07:48 +09:00
Florent Kermarrec 2be5205463 build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) 2018-10-04 08:17:44 +02:00
Tim 'mithro' Ansell 78414c0588 xilinx/viviado: Allow yosys for synthesis. 2018-10-03 21:58:03 -07:00
Tim 'mithro' Ansell d13ac3b3d5 cpu/mor1kx: Adding verilog include directory. 2018-10-03 21:57:24 -07:00
William D. Jones 9a44f08a3e build/platforms: Add ice40_hx8k_b_evn from Migen. 2018-10-03 20:53:33 -04:00
Tim 'mithro' Ansell dc7cd75757 build.xilinx: Run `phys_opt_design` and generate timing report. 
Makes the flow more similar to migen.
 2018-10-03 16:02:43 -07:00
Florent Kermarrec 948527b0fe cores/cpu: revert vexriscv (it seems there is a regression in last version) 2018-10-02 12:30:11 +02:00
Florent Kermarrec 15bca4535f targets/sim: fix integrated_main_ram_size when with_sdram 2018-10-02 11:31:08 +02:00
Florent Kermarrec 6e327cda26 bios/sdram: rewrite write_leveling (simplify and improve robustness) 2018-10-01 15:38:19 +02:00
Florent Kermarrec 975be6686f platforms/genesys2: add eth clock timing constraint 2018-10-01 15:37:34 +02:00
Florent Kermarrec 934a5da559 soc/cores/clock: add expose_drp on S7PLL/S7MMCM 2018-09-28 13:02:10 +02:00
enjoy-digital 9097573e71
Merge pull request #109 from cr1901/xip-improve 
Improve XIP Support
 2018-09-25 15:32:04 +02:00
Florent Kermarrec 082b03016c targets: use new clock abstraction on all 7-series targets 2018-09-25 09:31:30 +02:00
Florent Kermarrec 74e74dc0e7 soc/cores/clock: different clkin_freq_range for pll and mmcm 2018-09-25 09:09:47 +02:00
Florent Kermarrec 91d8cc2d6a soc/cores/clock: different vco_freq_range for pll and mmcm 2018-09-25 09:04:38 +02:00
Florent Kermarrec 6cd954940c soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG) 2018-09-25 08:36:18 +02:00
Florent Kermarrec 912ca3236b soc/cores/clock: create specific S7IDELAYCTRL module 2018-09-24 23:22:59 +02:00
Florent Kermarrec baec87f530 soc/cores/clock: add S7MMCM support 2018-09-24 23:20:12 +02:00
Florent Kermarrec ef40524924 soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest) 2018-09-24 22:58:23 +02:00