fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
1fd189512f
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
2015-05-08 23:10:08 +02:00
da711ad5f1
liteusb: add simple example design with wishbone bridge and software to control it
2015-05-02 18:21:18 +02:00
e9ef11620f
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)
2015-05-02 16:22:45 +02:00
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
1e1f7ce30e
liteusb: more pep8 (when convenient), should be almost OK
2015-04-13 14:47:44 +02:00
f10e873063
liteusb: pep8 (E265)
2015-04-13 14:37:39 +02:00
4974fd6bc9
liteusb: pep8 (E302)
2015-04-13 14:27:31 +02:00
cb473ddb6e
liteusb: pep8 (replace tabs with spaces)
2015-04-13 14:09:58 +02:00
20207c9c32
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
2015-03-22 11:11:37 +01:00
ed5746a1fe
liteusb: fix imports
2015-03-22 10:56:29 +01:00
b305b7828a
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
2015-03-02 08:36:39 +01:00
b647fe5823
merge liteusb
2015-02-28 11:16:16 +01:00
Florent Kermarrec