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2722 commits

Author SHA1 Message Date
Florent Kermarrec
470b6873ca interconnect/csr/EventManager: simpifly/cleanup code that documents CSRs and always enable documentation. 
A read_only mode has been added to CSRStatus to allow enabling writes on pending register and get the written
data used to clear events.
 2020-11-18 13:06:55 +01:00
Florent Kermarrec
30b2f187f4 soc/integration/builder: add generate_doc parameter and --doc args to builder_args. 
This allows generating the documentation easily from target files with --doc.
 2020-11-18 11:37:47 +01:00
enjoy-digital
b8b6fe2165
Merge pull request #699 from betrusted-io/document_events 
Create EventManager option for documented bits
 2020-11-18 11:06:04 +01:00
Leon Schuermann
778afb45d2 Add SoC timer peripheral timer-uptime CLI parameter 
This allows enabling the uptime register in the timer core from the
command line.
 2020-11-17 23:29:11 +01:00
Jędrzej Boczar
3bd5d6cc0e software/liblitedram: fix issues with command/write delays not being incremented. 2020-11-17 16:26:37 +01:00
bunnie
10256aa109 resolve xobs review comments 2020-11-17 05:10:16 +08:00
bunnie
377794748b add API to turn on documentation in I2S block for interrupts 2020-11-17 04:55:46 +08:00
bunnie
3dc18efe70 make documented events optional 2020-11-15 23:18:46 +08:00
bunnie
5d6c851f32 try to fix issue with unnamed sources 2020-11-15 22:03:23 +08:00
bunnie
ea80e9ef32 improve documentation strings, try to handle unnamed events better 2020-11-15 21:50:26 +08:00
bunnie
6a0a896e96 improve documentation output 2020-11-15 17:07:33 +08:00
bunnie
6deb750d6e Improve soc.svd output for eventmanager events 
Right now no data is created for which bit means what in
the soc.svd file. Attempt to extend event manager finalization
to use "fields" instead of bit positions, so that the SVD
file can auto-generate the events correctly.
 2020-11-15 16:33:14 +08:00
Florent Kermarrec
05f83ca978 tools/litex_term: minor cleanups (cosmetic). 2020-11-13 11:12:35 +01:00
Florent Kermarrec
5097b7ae5c boards: keep up to date with litex-boards, remove pcie_screamer target. 2020-11-12 18:16:56 +01:00
Florent Kermarrec
103c7e90a5 integration/soc/LiteXSoC: add initial add_pcie integration method. 2020-11-12 16:07:40 +01:00
Florent Kermarrec
7a4b26d2ba tools/litex_json2dts: fix missing {. 2020-11-12 14:45:46 +01:00
Florent Kermarrec
9c0f687922 build/generic_platform: use script filename as name when no Platform file. 2020-11-11 09:45:21 +01:00
Florent Kermarrec
275932f56c gen/fhdl/verilog: improve clock domain error reporting. 2020-11-10 13:27:29 +01:00
Florent Kermarrec
2741fc2ba5 build/generic_programmer: add call method that raises OSError when failing and use it on specific programmers. 
This will avoid programming errors to be silently ignored and will raise the following error:

OSError: Error occured during OpenOCD's call, please check:
- OpenOCD installation.
- access permissions.
- hardware and cable.
 2020-11-10 10:22:57 +01:00
Florent Kermarrec
a5bdfe3f4c software/i2c: add i2c_scan command. 2020-11-10 09:47:28 +01:00
Florent Kermarrec
ce9f24748f soc/cores/bitbang/I2C: use Tristate on SDL/SDA and only drive low (rely on I2C Pull-Ups for high). 2020-11-10 09:46:43 +01:00
Florent Kermarrec
221ea4c31a tools/remote/comm_udp: revert try/except (was probably needed with CommUDP's max_length = 4). 2020-11-09 16:36:04 +01:00
Florent Kermarrec
5aa70d975c tools/litex_server: revert CommUDP's max length to 1 (needs more testing). 2020-11-09 16:35:04 +01:00
Florent Kermarrec
1d04b1dd83 software/liblitesdcard: Operate the SDCard in 3.3V/High Speed. 
SDR50/Driver strength configuration is for 1.8V that is no longer supported
(for simplicity).
 2020-11-09 15:39:54 +01:00
Florent Kermarrec
b3a42d76ce cores/cpu/microwatt: fix non irq variant, add standard+irq/"standard+gdhl+irq variants, move XICSSlave after CPU class. 2020-11-09 13:31:11 +01:00
enjoy-digital
3673f38d63
Merge pull request #653 from gsomlo/gls-dt-cpufreq 
RFC: json2dts: set CPU clock-frequency and SoC bus-frequency
 2020-11-09 12:40:15 +01:00
enjoy-digital
ecaf69fe78
Merge pull request #688 from rprinz08/master 
Fix check for wrong named attributes
 2020-11-09 11:22:08 +01:00
Florent Kermarrec
0627c01d89 soc/cores/spi_opi: move add_timing_constraints after __init__ to ease readability (first describe the logic then add the constraints). 2020-11-09 11:15:00 +01:00
enjoy-digital
5587ee5eea
Merge pull request #690 from betrusted-io/master 
Add arbitrary command (eg. write) capability to SPI DOPI
 2020-11-09 11:12:13 +01:00
enjoy-digital
80883ef37e
Merge pull request #689 from DurandA/patch-7 
libcompiler_rt: Remove duplicate mulsi3.o in Makefile
 2020-11-09 11:08:29 +01:00
Florent Kermarrec
50a47f551e soc/cores: create ram directory and move SPRAM/LRAM implementation to it. 
Will ease maintenance and future additions similarly to clock wrappers. Provide
retro-compatibily layer for Up5kSPRAM that we could remove after next release.
 2020-11-09 11:04:31 +01:00
Florent Kermarrec
ea8be6adcd targets/kcu105: add missing AsyncResetSynchronizer import. 2020-11-09 10:40:36 +01:00
Florent Kermarrec
14e196ab5d soc/cores/clock: create directory and split code in separate files to ease maintenance/adding new devices. 
clock.py was originally created/prototyped for 7-Series FPGAs, but has since been extended to almost all
FPGA devices supported by LiteX making it large enough to justify the split.

soc/cores/clock/__init__.py provides the retro-compatibily layer.
 2020-11-09 10:33:12 +01:00
bunnie
036ea48a4d update constraints to be in-line with litex methodology 2020-11-09 16:43:01 +08:00
davidcorrigan714
a6fd7b5d37 Lattice NX PLL Support 2020-11-08 20:34:10 -06:00
bunnie
b59711f89f Merge remote-tracking branch 'origin/master' 2020-11-08 14:35:41 +08:00
Arnaud Durand
2c36098f45
libcompiler_rt: Remove duplicate mulsi3.o in Makefile 2020-11-08 03:21:39 +01:00
rprinz08
09ecd9abc9 Make commUDP more reliable in case of bad Ethernet connection 2020-11-07 11:32:50 +01:00
rprinz08
1c039389f2 Fix check for wrong named attributes 2020-11-07 11:13:51 +01:00
bunnie
d892c6f8f5 minor bug fixes in spi writing; USB-based flashing is not working 2020-11-07 03:57:46 +08:00
Florent Kermarrec
9359aa0688 tools/litex_server: revert CommUDP's max length to 4 now that https://github.com/enjoy-digital/liteeth/issues/52 is fixed). 2020-11-06 19:50:25 +01:00
Florent Kermarrec
9fe3a42072 software/liblitedra/sdram: minor cleanup, use identical delay after each delay increment. 2020-11-06 16:11:25 +01:00
Florent Kermarrec
d1ef64f9fd tools/litex_server: revert CommUDP's max_length to 1. 
https://github.com/enjoy-digital/liteeth/issues/52 needs to be investigated before enabling _read_merger
on UDP.
 2020-11-06 13:01:56 +01:00
Florent Kermarrec
996be95725 tools/litex_sim: also add CPU's dbus to analyzer_signals (to demonstrate triggers in wiki). 2020-11-06 12:49:43 +01:00
bunnie
fc59bcd833 add facility for burst writing and fix pp4b command bug 2020-11-06 04:43:23 +08:00
Florent Kermarrec
61c009a393 revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00
Florent Kermarrec
c088cd5d22 cores/clock: only use locked on AsyncResetSynchronizer (already falling on reset) and add delay to reset to prevent interlocks with BIOS reboot command on Xilinx devices. 2020-11-05 19:43:11 +01:00
Florent Kermarrec
3e47a6e48b get_data_mod: fix error message when module not found (pythondata modules are named only with "-" and not "_"). 2020-11-05 15:58:32 +01:00
Florent Kermarrec
65f19b5c4a integration/soc/add_sdram: add with_bist parameter to add LiteDRAM's BIST. 
sdram_bist command will then be available in the BIOS:

litex> sdram_bist
sdram_bist <burst_length> <random>
litex> sdram_bist 256 0
Starting SDRAM BIST with burst_length=256 and random=0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455            0            0
            473             455           25            0
            473             455           50            0
            473             455           75            0
            473             455          100            0
            473             455          125            0
            473             455          150            0
            473             455          175            0
            473             455          200            0
            473             455          225            0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455          250            0
            473             455          275            0
            473             455          300            0
            473             455          325            0
            473             455          350            0
            473             455          375            0
            473             455          400            0
            473             455          425            0
            473             455          450            0
            473             455          475            0
WR-SPEED(MiB/s) RD-SPEED(MiB/s)  TESTED(MiB)       ERRORS
            473             455          500            0
            473             455          525            0
            473             455          550            0
            473             455          575            0
            473             455          600            0
            473             455          625            0

litex>
 2020-11-05 13:41:37 +01:00
Florent Kermarrec
97b35a0771 software/liblitedram/bist: update generator/checker control to configure end CSR. 2020-11-05 13:39:48 +01:00
Florent Kermarrec
3dffdbf628 build/xilinx: add missing \n on error reporting. 2020-11-04 11:32:25 +01:00
Florent Kermarrec
897b2ea412 boards/targets: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:15:04 +01:00
Florent Kermarrec
ffc554dede soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents. 2020-11-04 10:58:16 +01:00
Florent Kermarrec
2c504783ca bios/cmd/cmd_bios: add leds command to set leds value. 
Can be used as a first/simple/visual example to start interacting with the hardware from the CPU/BIOS.
 2020-11-04 10:22:14 +01:00
Florent Kermarrec
db836e8e5d build: add toolchain check before running build script and improve error reporting. 2020-11-04 09:42:18 +01:00
bunnie
6e806ce60c refactor SPI DOPI interface to support arbitrary commands, not jsut reads 
lays the groundwork for doing page programming and sector erasing
 2020-11-04 04:39:47 +08:00
Florent Kermarrec
f8cadc7b04 software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable). 2020-11-03 19:20:43 +01:00
enjoy-digital
b8d48385f6
Merge pull request #684 from sergachev/master 
cores/cpu/zynq7000: fix axi hp slave registration
 2020-11-03 14:53:10 +01:00
Florent Kermarrec
99b103998d software/liblitedram: expose sdram_bist_loop. 2020-11-03 13:03:45 +01:00
Florent Kermarrec
9d94bcdef7 boards/platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:59:12 +01:00
Florent Kermarrec
b63e2d3b94 boards/platforms: remove pcie_screamer (we'll add it to litex-boards). 2020-11-03 10:53:26 +01:00
Ilia Sergachev
cc652dda77 cores/cpu/zynq7000: fix axi hp slave registration 2020-11-03 00:55:16 +01:00
Florent Kermarrec
081d883421 targets/kc705: revert sys_clk_freq to 150MHz. 2020-11-02 19:52:28 +01:00
Florent Kermarrec
c1c095fdd4 targets/nexys_video: add SATA support. 2020-11-02 19:46:11 +01:00
Florent Kermarrec
cc95d89a6f boards/kc705: update sata integration. 2020-11-02 19:01:10 +01:00
Florent Kermarrec
d18157edde software/bios/cmd_litesata: add sata_init/sata_write commmands. 2020-10-30 15:38:45 +01:00
Florent Kermarrec
cb1badb173 software/liblitesata: add sata_write and update #ifdefs. 2020-10-30 15:38:17 +01:00
Florent Kermarrec
638d28d8d4 soc/sata: fix typo in Mem2Sector DMA. 2020-10-30 15:37:20 +01:00
Florent Kermarrec
060bbf1d59 soc/sata: add write support with LiteSATAMem2SectorDMA. 2020-10-30 12:20:12 +01:00
Florent Kermarrec
c4a6fe7d96 soc/sata: update SATA integration (LiteSATABlock2MemDMA renamed to LiteSATASector2MemDMA). 2020-10-30 12:09:34 +01:00
Florent Kermarrec
7bcf8cb752 software/liblitedram: switch to uint32_t (as workaround for #322) and expose burst_length/random parameters to sdram_bist command. 2020-10-29 18:31:47 +01:00
Florent Kermarrec
07503d22ac soc/software: move FatFs to libfatfs (avoid duplication in liblitesdcard/liblitesata). 2020-10-29 15:06:02 +01:00
Florent Kermarrec
b9ceed0f74 integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check. 2020-10-29 10:50:10 +01:00
Florent Kermarrec
e7ad705359 integration/soc: add initial SATA integration with DMA read support. 2020-10-29 10:15:46 +01:00
bunnie
e8c39ec3d2 add generic command processing state machine 
facilitates page writes and sector erases
first commit, debugging now commencing
 2020-10-29 05:09:18 +08:00
Florent Kermarrec
9b123f7c9a software/liblitesata: implement sata_init with new CSR registers. 2020-10-28 19:55:19 +01:00
Florent Kermarrec
1fca7b9a91 software/liblitesata/sata_read: handle errors. 2020-10-28 18:59:36 +01:00
Florent Kermarrec
2bb46b305b software/liblitesata: fix warning, typo, add TODO. 2020-10-27 09:39:01 +01:00
Florent Kermarrec
c0ba03ef66 targets/kc705: add initial SATA support. 2020-10-26 15:14:40 +01:00
Florent Kermarrec
4127af36b5 soc/software: add initial minimal LiteSATA support (allow booting from SATA drive). 2020-10-26 15:13:56 +01:00
bunnie
37f2ebe675 add responder for type 0 cti, so that wb debug access works 2020-10-25 17:50:56 +08:00
Florent Kermarrec
c474272f53 soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why. 2020-10-23 14:33:24 +02:00
Florent Kermarrec
e94876753d soc/cores/icap: add back missing add_csr (was missing after adding add_reload method). 2020-10-23 08:00:43 +02:00
Florent Kermarrec
0dec446434 tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli. 
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
 2020-10-22 17:45:45 +02:00
Florent Kermarrec
30b226f895 soc/intergration/export: additional name override fix. 2020-10-22 08:55:14 +02:00
enjoy-digital
abdc8bb26e
Merge pull request #681 from Disasm/fix-svd-soc-name 
Fix SoC name in SVD generator
 2020-10-22 08:53:32 +02:00
Florent Kermarrec
4eb634ba2d soc/interconnect/csr: fix CSRAccess values check. 2020-10-21 21:43:08 +02:00
enjoy-digital
e7b33a9ea8
Merge pull request #680 from daveshah1/dave/radiant-portname-fix 
radiant: Use {} string for bus port names
 2020-10-21 21:23:05 +02:00
enjoy-digital
7bbde6d05a
Merge pull request #679 from DurandA/patch-6 
Add integer limits to stdint.h
 2020-10-21 21:22:37 +02:00
Florent Kermarrec
c430587e91 soc/interconnect/stream/Shifter: add shift signal as optional parameter. 2020-10-21 15:52:53 +02:00
Vadim Kaushan
e4997295bd
Fix SoC name in SVD generator 
The name was overwritten with one of the CSR region names
 2020-10-21 16:40:35 +03:00
David Shah
66eb38cf84 radiant: Escape bus port names 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-21 14:05:33 +01:00
Florent Kermarrec
5a6b8f452d soc/interconnect/stream: add Shifter. 
Useful to shift stream data (ex for SerDes alignment).
 2020-10-21 12:47:55 +02:00
Florent Kermarrec
ad04365e20 soc/cores/code_8b10b: add K helper. 2020-10-21 09:49:38 +02:00
Florent Kermarrec
e91ec2ed83 soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams). 
With improvements to handle backpressure on non-continous streams.
 2020-10-21 09:29:21 +02:00
Arnaud Durand
eb26d09dbe Add integer limits to stdint.h 2020-10-21 01:48:29 +02:00
Florent Kermarrec
918a0d95ba platforms/targets: keep up to date with litex-boards. 2020-10-20 12:00:33 +02:00
enjoy-digital
84c358889d
Merge pull request #677 from madscientist159/master 
Add initial interrupt support for Microwatt in LiteX
 2020-10-20 08:56:39 +02:00
enjoy-digital
72140f6df9
Merge pull request #674 from daveshah1/radiant-yosys-synth 
build/radiant: Allow synthesis with Yosys
 2020-10-20 08:15:36 +02:00
Raptor Engineering Development Team
90d71ec247 Add initial interrupt support for Microwatt in LiteX 
There is a conflict between the LiteX way of doing things and the POWER
way of handling interrupt tables.  LiteX expects to be able to put a ROM
at address 0 and load an application into RAM at a higher address; POWER
is architected to jump to exception handlers at 0x100...0x1000.

As a result of this, we have taken the approach of placing generic exception
handler entry / exit routines into ROM, and reserving a single pointer in
SRAM to determine the C ISR handler location.  If no application is loaded,
this pointer is set to the BIOS ROM ISR.  When an application loads, before
reenabling interrupts, it needs to set __rom_isr_address to the address of
the application's ISR, otherwise the BIOS ROM ISR will continue to be used.

Tested to operate with the built-in UART in IRQ mode, both in BIOS and in
loaded RAM application.
 2020-10-16 14:49:05 -05:00