Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
6359 commits 42 branches 14 tags 31 MiB
Commit graph

2722 commits

Author SHA1 Message Date
Florent Kermarrec
3dffdbf628 build/xilinx: add missing \n on error reporting. 2020-11-04 11:32:25 +01:00
Florent Kermarrec
897b2ea412 boards/targets: add rst signal to CRG to allow full reset of the SoC on reboot command. 2020-11-04 11:15:04 +01:00
Florent Kermarrec
ffc554dede soc/integration/core: Connect SoCController's reset to CRG.rs do full reset of the SoC with reboot when signals are presents. 2020-11-04 10:58:16 +01:00
Florent Kermarrec
2c504783ca bios/cmd/cmd_bios: add leds command to set leds value. 
Can be used as a first/simple/visual example to start interacting with the hardware from the CPU/BIOS.
 2020-11-04 10:22:14 +01:00
Florent Kermarrec
db836e8e5d build: add toolchain check before running build script and improve error reporting. 2020-11-04 09:42:18 +01:00
bunnie
6e806ce60c refactor SPI DOPI interface to support arbitrary commands, not jsut reads 
lays the groundwork for doing page programming and sector erasing
 2020-11-04 04:39:47 +08:00
Florent Kermarrec
f8cadc7b04 software/liblitesata/init: avoid reset when SATA PHY already ready (gateware is already hotplug capable). 2020-11-03 19:20:43 +01:00
enjoy-digital
b8d48385f6
Merge pull request #684 from sergachev/master 
cores/cpu/zynq7000: fix axi hp slave registration
 2020-11-03 14:53:10 +01:00
Florent Kermarrec
99b103998d software/liblitedram: expose sdram_bist_loop. 2020-11-03 13:03:45 +01:00
Florent Kermarrec
9d94bcdef7 boards/platforms: cleanup pass to uniformize comments/separators/orders. 2020-11-03 10:59:12 +01:00
Florent Kermarrec
b63e2d3b94 boards/platforms: remove pcie_screamer (we'll add it to litex-boards). 2020-11-03 10:53:26 +01:00
Ilia Sergachev
cc652dda77 cores/cpu/zynq7000: fix axi hp slave registration 2020-11-03 00:55:16 +01:00
Florent Kermarrec
081d883421 targets/kc705: revert sys_clk_freq to 150MHz. 2020-11-02 19:52:28 +01:00
Florent Kermarrec
c1c095fdd4 targets/nexys_video: add SATA support. 2020-11-02 19:46:11 +01:00
Florent Kermarrec
cc95d89a6f boards/kc705: update sata integration. 2020-11-02 19:01:10 +01:00
Florent Kermarrec
d18157edde software/bios/cmd_litesata: add sata_init/sata_write commmands. 2020-10-30 15:38:45 +01:00
Florent Kermarrec
cb1badb173 software/liblitesata: add sata_write and update #ifdefs. 2020-10-30 15:38:17 +01:00
Florent Kermarrec
638d28d8d4 soc/sata: fix typo in Mem2Sector DMA. 2020-10-30 15:37:20 +01:00
Florent Kermarrec
060bbf1d59 soc/sata: add write support with LiteSATAMem2SectorDMA. 2020-10-30 12:20:12 +01:00
Florent Kermarrec
c4a6fe7d96 soc/sata: update SATA integration (LiteSATABlock2MemDMA renamed to LiteSATASector2MemDMA). 2020-10-30 12:09:34 +01:00
Florent Kermarrec
7bcf8cb752 software/liblitedram: switch to uint32_t (as workaround for #322) and expose burst_length/random parameters to sdram_bist command. 2020-10-29 18:31:47 +01:00
Florent Kermarrec
07503d22ac soc/software: move FatFs to libfatfs (avoid duplication in liblitesdcard/liblitesata). 2020-10-29 15:06:02 +01:00
Florent Kermarrec
b9ceed0f74 integration/soc/sata: fix sys_clk_freq vs sata_freq_clk check. 2020-10-29 10:50:10 +01:00
Florent Kermarrec
e7ad705359 integration/soc: add initial SATA integration with DMA read support. 2020-10-29 10:15:46 +01:00
bunnie
e8c39ec3d2 add generic command processing state machine 
facilitates page writes and sector erases
first commit, debugging now commencing
 2020-10-29 05:09:18 +08:00
Florent Kermarrec
9b123f7c9a software/liblitesata: implement sata_init with new CSR registers. 2020-10-28 19:55:19 +01:00
Florent Kermarrec
1fca7b9a91 software/liblitesata/sata_read: handle errors. 2020-10-28 18:59:36 +01:00
Florent Kermarrec
2bb46b305b software/liblitesata: fix warning, typo, add TODO. 2020-10-27 09:39:01 +01:00
Florent Kermarrec
c0ba03ef66 targets/kc705: add initial SATA support. 2020-10-26 15:14:40 +01:00
Florent Kermarrec
4127af36b5 soc/software: add initial minimal LiteSATA support (allow booting from SATA drive). 2020-10-26 15:13:56 +01:00
bunnie
37f2ebe675 add responder for type 0 cti, so that wb debug access works 2020-10-25 17:50:56 +08:00
Florent Kermarrec
c474272f53 soc/interconnect/stream: comment reset_less on payload since cause issue with LiteSATA, understand why. 2020-10-23 14:33:24 +02:00
Florent Kermarrec
e94876753d soc/cores/icap: add back missing add_csr (was missing after adding add_reload method). 2020-10-23 08:00:43 +02:00
Florent Kermarrec
0dec446434 tools/litex_client: add utils to dump FPGA identifier and registers and expose it as litex_cli. 
Dump FPGA identifier: litex_cli --ident
Dump FPGA registers: litex_cli --regs
 2020-10-22 17:45:45 +02:00
Florent Kermarrec
30b226f895 soc/intergration/export: additional name override fix. 2020-10-22 08:55:14 +02:00
enjoy-digital
abdc8bb26e
Merge pull request #681 from Disasm/fix-svd-soc-name 
Fix SoC name in SVD generator
 2020-10-22 08:53:32 +02:00
Florent Kermarrec
4eb634ba2d soc/interconnect/csr: fix CSRAccess values check. 2020-10-21 21:43:08 +02:00
enjoy-digital
e7b33a9ea8
Merge pull request #680 from daveshah1/dave/radiant-portname-fix 
radiant: Use {} string for bus port names
 2020-10-21 21:23:05 +02:00
enjoy-digital
7bbde6d05a
Merge pull request #679 from DurandA/patch-6 
Add integer limits to stdint.h
 2020-10-21 21:22:37 +02:00
Florent Kermarrec
c430587e91 soc/interconnect/stream/Shifter: add shift signal as optional parameter. 2020-10-21 15:52:53 +02:00
Vadim Kaushan
e4997295bd
Fix SoC name in SVD generator 
The name was overwritten with one of the CSR region names
 2020-10-21 16:40:35 +03:00
David Shah
66eb38cf84 radiant: Escape bus port names 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-21 14:05:33 +01:00
Florent Kermarrec
5a6b8f452d soc/interconnect/stream: add Shifter. 
Useful to shift stream data (ex for SerDes alignment).
 2020-10-21 12:47:55 +02:00
Florent Kermarrec
ad04365e20 soc/cores/code_8b10b: add K helper. 2020-10-21 09:49:38 +02:00
Florent Kermarrec
e91ec2ed83 soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams). 
With improvements to handle backpressure on non-continous streams.
 2020-10-21 09:29:21 +02:00
Arnaud Durand
eb26d09dbe Add integer limits to stdint.h 2020-10-21 01:48:29 +02:00
Florent Kermarrec
918a0d95ba platforms/targets: keep up to date with litex-boards. 2020-10-20 12:00:33 +02:00
enjoy-digital
84c358889d
Merge pull request #677 from madscientist159/master 
Add initial interrupt support for Microwatt in LiteX
 2020-10-20 08:56:39 +02:00
enjoy-digital
72140f6df9
Merge pull request #674 from daveshah1/radiant-yosys-synth 
build/radiant: Allow synthesis with Yosys
 2020-10-20 08:15:36 +02:00
Raptor Engineering Development Team
90d71ec247 Add initial interrupt support for Microwatt in LiteX 
There is a conflict between the LiteX way of doing things and the POWER
way of handling interrupt tables.  LiteX expects to be able to put a ROM
at address 0 and load an application into RAM at a higher address; POWER
is architected to jump to exception handlers at 0x100...0x1000.

As a result of this, we have taken the approach of placing generic exception
handler entry / exit routines into ROM, and reserving a single pointer in
SRAM to determine the C ISR handler location.  If no application is loaded,
this pointer is set to the BIOS ROM ISR.  When an application loads, before
reenabling interrupts, it needs to set __rom_isr_address to the address of
the application's ISR, otherwise the BIOS ROM ISR will continue to be used.

Tested to operate with the built-in UART in IRQ mode, both in BIOS and in
loaded RAM application.
 2020-10-16 14:49:05 -05:00
Raptor Engineering Development Team
af82abb807 Allow SoCCore instances to set maximum interrupt number 2020-10-16 14:48:04 -05:00
Florent Kermarrec
288306c86a software/liblitedram: add initial Build-In Self-Test software. 
To be used with LiteDRAM's BIST Generator/Checker, ex:

from litedram.frontend.bist import  LiteDRAMBISTGenerator, LiteDRAMBISTChecker
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.add_csr("sdram_generator")
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
self.add_csr("sdram_checker")
 2020-10-15 16:20:05 +02:00
Florent Kermarrec
c6f7f0210a soc/cores/spi_opi: expose dq/dq_copi to allow constrainting them from design. 2020-10-14 10:31:29 +02:00
David Shah
15dc97476c build/radiant: Allow synthesis with Yosys 
Signed-off-by: David Shah <dave@ds0.me>
 2020-10-13 12:11:48 +01:00
Florent Kermarrec
f0abc185e1 targets/sim: update sdram (manual cmd_latency no longer needed). 2020-10-12 18:47:09 +02:00
Florent Kermarrec
bc68351475 software/liblitedram: use SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE flag. 2020-10-12 16:05:44 +02:00
Florent Kermarrec
c596135274 bios/cmd/cmd_litedram: add sdram_test command. 2020-10-12 13:52:15 +02:00
Florent Kermarrec
d4d4ca53b0 software/liblitedram/sdram.c: move activate/precharge to sdram_write_read_check_test_pattern, change second seed. 2020-10-12 13:00:44 +02:00
Florent Kermarrec
d1f04e67c5 software/liblitedram: use 2 cycles increment on write bitslip (for tCK steps). 2020-10-12 10:58:43 +02:00
Florent Kermarrec
3d5bc29dd1 software/liblitedram: add initial write latency calibration. 2020-10-09 20:04:16 +02:00
Florent Kermarrec
3518223c84 software/liblitedram: add functions to simplify read_leveling and do the test with 2 seeds. 
Doing the test with 2 seeds prevents the test to success if previous content in DRAM was
still the expected one (ex after a sdram_cal command that succeded).
 2020-10-09 15:50:44 +02:00
Florent Kermarrec
69177c9251 software/liblitesdram: add initial support for write leveling bitslip (configurable via bios commands). 2020-10-08 19:38:57 +02:00
Florent Kermarrec
004924a319 soc/interconnect/csr: expose re on CSRStatus (to allow triggering actions on CSRStatus writes). 2020-10-08 11:34:57 +02:00
Florent Kermarrec
b904aa7d18 libbase/memtest: simplify logs and add test size to memtest/memspeed banner. 2020-10-08 09:11:28 +02:00
Florent Kermarrec
e4fe0d9ef4 soc/cores/spi_flash: fix with_bitbang=False compilation. 2020-10-07 19:32:10 +02:00
Florent Kermarrec
375b6f2dc7 soc/cores/spi_flash: fix Dual mode compilation. 2020-10-07 19:28:13 +02:00
Florent Kermarrec
a2b71fde4a soc: change default CSR bus data-width to 32. 
A CSR bus data-width of 32 has been validated on very various design and is
now recommended. It provides better performance without impacting resource
usage (even on iCE40).
 2020-10-07 16:38:49 +02:00
Florent Kermarrec
4f30a5b8e5 libbase/memtest: add memtest_data_speed function that prints speed in B/KiB/MiB/GiB/s depending the value. 2020-10-07 13:01:14 +02:00
Florent Kermarrec
0a80e4c3d6 libbase/memtest: revert previous printf (the informations are provided below and this make it too verbose). 2020-10-07 12:42:58 +02:00
enjoy-digital
5e2a4efac6
Merge pull request #665 from fidergo-stephane-gourichon/more_precise_log 
More precise memory performance test.
 2020-10-07 12:38:44 +02:00
enjoy-digital
83b4447f0e
Merge pull request #662 from fidergo-stephane-gourichon/dfu-util_with_-R 
Unconditionally ask dfu-util to "Issue USB Reset"
 2020-10-07 12:37:53 +02:00
Florent Kermarrec
ad7671f811 soc/cores/icap/ICAP: add with_csr parameter and add_reload method to allow reloading the FPGA from the logic. 2020-10-06 17:38:39 +02:00
Gabriel Somlo
026d40ffab bios: add command returning card-detect pin status 2020-10-05 14:32:06 -04:00
enjoy-digital
6916674ff6
Merge pull request #664 from antmicro/symbiflow_a100T 
build/xilinx/symbiflow: Add xc7a100tscg324-1 to supported devices
 2020-10-05 19:25:18 +02:00
enjoy-digital
81257da9b4
Merge pull request #663 from fidergo-stephane-gourichon/fix_crash_on_minimal_cpu 
Fix SoC CPU crash on minimal variants on call to flush_cpu_dcache().
 2020-10-05 19:24:43 +02:00
enjoy-digital
1a603b3fee
Merge pull request #654 from pepijndevos/gowin 
Build support for Gowin
 2020-10-05 19:23:47 +02:00
Stephane Gourichon
f71275a3f1 Show speeds in bytes per second. 
Forcing megabytes per second for everyone does not make sense.
Showing bytes per second allows to distinguish between low performance and a performance measurement bug.
Anyway previous code claims speeds were in MiB/s, they were not, actually MB/s.
 2020-10-05 18:46:05 +02:00
Stephane Gourichon
cbbbb3f468 Only display write speed if write test actually performed. 2020-10-05 18:43:45 +02:00
Stephane Gourichon
5b0ced00b5 Confirm parameters in log. 2020-10-05 17:58:44 +02:00
Stephane Gourichon
48638f936b Fix SoC CPU crash on minimal variants on call to flush_cpu_dcache(). 
Generated soc.h says for example

but code tester for CONFIG_CPU_VARIANT_MIN not MINIMAL.
Attempted to run instruction unknown to this CPU, most likely cause of hang.
 2020-10-05 17:16:35 +02:00
Stephane Gourichon
e47f84ea79 Unconditionally ask dfu-util to "Issue USB Reset signalling once we're finished". 
Some host machines need it.
If issuing -R always does not cause any trouble, then do it.
 2020-10-05 17:16:10 +02:00
enjoy-digital
aebe08d841
Merge pull request #661 from yetifrisstlama/fix_stream2wishbone 
Fix stream2wishbone
 2020-10-05 17:16:04 +02:00
Robert Winkler
ff4afda305 build/xilinx/symbiflow: Add xc7a100tscg324-1 to supported devices 
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-10-05 17:02:51 +02:00
Michael Betz
acdfae202b Stream2Wishbone: drive sink.ready line 2020-10-04 18:19:39 -07:00
Michael Betz
6e3e979a0b serial2tcp.c json error handling, respect rx.ready 2020-10-04 18:17:28 -07:00
Shawn Anastasio
fa82d97aa5 cores/cpu: Add riscv*-unknown-linux-gnu triple, fix riscv-linux-gnu 
Add riscv*-unknown-linux-gnu to known triples, and fix the existing
riscv-linux-gnu by removing the incorrect -gcc suffix from the
triple.
 2020-10-02 18:31:48 -05:00
Shawn Anastasio
6fd48ca2ce software: Use -fno-stack-protector 
This allows riscv*-gnu-linux toolchains to be used to build LiteX
software. Without this, references to undefined stack guard symbols
get generated and linking fails.
 2020-10-02 13:42:16 -05:00
Gabriel Somlo
c77da3a8bc RFC: json2dts: set CPU clock-frequency and SoC bus-frequency 
FIXME: timebase-frequency isn't to be used as the raw CPU clock, so
on vexriscv we might want to re-evaluate also setting *that* to the
`CONFIG_CLOCK_FREQUENCY`. Decide whether to keep the SoC's
`bus-frequency` cell, or whether to go with the CPU's `clock-frequency`
only.
 2020-10-01 06:59:45 -04:00
Florent Kermarrec
ba2ff8cf71 tools/litex_sim: update get_sdram_phy_settings (rd/wrcmdphase no longer exposed as PhySettings). 2020-10-01 11:27:33 +02:00
Florent Kermarrec
2b62802961 tools/litex_sim: minor review cleanup. 2020-10-01 10:36:37 +02:00
Florent Kermarrec
23e319732c tools/litex_server: minor review cleanup. 2020-10-01 10:35:11 +02:00
Vamsi Vytla
e8c0360fa5
tools/{litex_sim, litex_server}.py: Minor clean-up (#657) 
Enable litex_server debug and create function to add for litex_sim args.
 2020-10-01 10:32:44 +02:00
Pepijn de Vos
890ccaf4bd support writing bitstream to flash 2020-10-01 08:39:32 +02:00
Florent Kermarrec
29bff18e69 software/liblitedram: add SDRAM CL/CWL printf to BIOS. 2020-09-30 19:00:12 +02:00
Florent Kermarrec
f476b32ada software/liblitedram: rename SDRAM_TEST_SIZE to MEMTEST_DATA_SIZE (since used in benchs to force test size). 2020-09-30 18:34:48 +02:00
Florent Kermarrec
f7e49cc23a software/liblitedram: add SDRAM_TEST_SIZE (2MiB as previously defined in memtest). 2020-09-30 18:02:07 +02:00
Florent Kermarrec
fdf7981f40 software/libbase/memtest: remove size restriction and don't execute memspeed. 2020-09-30 17:49:51 +02:00
Florent Kermarrec
ed21c983cb Merge branch 'master' of http://github.com/enjoy-digital/litex 2020-09-30 17:29:04 +02:00
Florent Kermarrec
c154f1cbb2 software/liblitedram: add support for dynamic read/write phase and add command to BIOS to force them. 2020-09-30 17:09:19 +02:00
enjoy-digital
6f136f9faa
Merge pull request #655 from betrusted-io/svd_memregion 
add memory regions to soc.svd
 2020-09-30 11:43:14 +02:00
Konrad Beckmann
39d144626b Fix build issue where sdram_leveling is not found 
4f76656 rewrote how sdram_leveling() was called, leading
to linking problems for targets with sdram but with
write leveling disabled, e.g. ulx3s.
 2020-09-29 22:49:41 +02:00
Florent Kermarrec
a9234a8793 software/liblitedram: allow cmd_delay adjustment even when enforced by the phy. 2020-09-29 16:02:21 +02:00
Pepijn de Vos
eca5a25e27 add dummy attr_translate 2020-09-29 15:55:07 +02:00
Florent Kermarrec
4f76656018 software/liblitedram: simplify vtc/hardware/software controls. 
- move vtc control to sdram_software_control_on/off.
- remove sdram_calibration (duplicate of sdram_leveling).
- be sure to call sdram_software_control_on/off before all litedram bios commands.
 2020-09-29 15:40:26 +02:00
Pepijn de Vos
dd2b1f21f0 typo and dead code 2020-09-29 15:24:36 +02:00
Florent Kermarrec
e4555df095 tools/litex_server/pcie: enable pcie device if not already enabledd. 
Avoid having to do it manually or through a driver.
 2020-09-29 13:38:19 +02:00
Florent Kermarrec
bc5873f78c tools/litex_server/pcie: allow passing pcie bar as reported by lspci. 
ex:
$lspci
[...]
06:00.0 RF controller: Xilinx Corporation Device 7022 (rev 01)

sudo litex_server --pcie --pcie-bar=06:00.0
 2020-09-29 13:10:05 +02:00
Florent Kermarrec
6d07f01f5b tools/litex_client/RemoteClient: allow use without local csr.csv file. 
In some case, we just want to access MMAP manually without having the csr.csv file:
wb = RemoteClient()
wb.open()
wb.read(0x40000000)
wb.close()
 2020-09-29 13:01:44 +02:00
bunnie
7b42992383 add <memoryRegions> outer tag to series of <memoryRegion> for future proofing 2020-09-29 14:11:55 +08:00
bunnie
4a94bb78f6 add memory regions to soc.svd 
svd2rust does not recognize memory regions, but we'd like to
make an access crate for Rust that does.

This patch adds memory regions to soc.svd using the "vendorExtensions"
tag, as specified in https://www.keil.com/pack/doc/cmsis/SVD/html/svd_Format_pg.html

The vendorExtensions is added as a block after the Peripherals level, and has a format
like this:

```xml
        <memoryRegion>
            <name>SRAM</name>
            <baseAddress>0x10000000</baseAddress>
            <size>0x00020000</size>
        </memoryRegion>
        <memoryRegion>
            <name>VEXRISCV_DEBUG</name>
            <baseAddress>0xEFFF0000</baseAddress>
            <size>0x00000100</size>
        </memoryRegion>
        <memoryRegion>
            <name>CSR</name>
            <baseAddress>0xF0000000</baseAddress>
            <size>0x00040000</size>
        </memoryRegion>
```
 2020-09-29 01:30:09 +08:00
Pepijn de Vos
95564b7475 change name->devicename, working bios 2020-09-28 17:49:41 +02:00
Pepijn de Vos
c0fa4fd1f4 initial build support for Gowin 2020-09-28 13:12:07 +02:00
Florent Kermarrec
a1c023b900 software/bios/cmds/cmd_litedram: enable sdram_software_control before sdram_mode_register_write. 2020-09-24 14:58:42 +02:00
Florent Kermarrec
90a2b80b6a software/liblitedram/sdram_write_leveling_rst_cmd_delay: fix printf location (do it before taps is decremented). 2020-09-24 13:54:08 +02:00
Florent Kermarrec
7617a82fe6 targets/kcu105: create specific cd_eth for ethernet. 2020-09-24 10:27:48 +02:00
Florent Kermarrec
a3c616028e software/liblitedram/sdram: fix cmd_delays -> dat_delays. 2020-09-23 19:43:28 +02:00
Gabriel Somlo
8e7596d330 liblitesdcard/sdcard.c: ensure effective sdcard clock is <= requested 
With the way the clock divider is currently calculated, it is
possible for the effective sdcard clock to end up *higher* than
the requested `clk_freq` value.

Calculate the divider starting with the `CONFIG_CLOCK_FREQUENCY/clk_freq`
ratio which is then rounded up to the nearest power-of-two, ensuring
that the resulting, effective clock frequency is <= to the requested
frequency.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-09-22 15:15:50 -04:00
Florent Kermarrec
ac32b92e9f targets/kcu105: add etherbone. 2020-09-22 18:31:06 +02:00
Florent Kermarrec
a601415bf0 software/liblitedram: add functions/commands to reset and force cmd/dat write leveling delays. 
Useful to investigate/speed-up new board support.
 2020-09-21 19:53:34 +02:00
Florent Kermarrec
a39660fa99 software/liblitedram/sdram.c: fix typo. 2020-09-17 18:19:12 +02:00
Florent Kermarrec
a0d66dd60e software/liblitesdcard/sdcard: move busy_wait in sdcard_wait_cmd_done (fixes sdcardboot being stuck since code refactoring) and reduce busy_wait value. 2020-09-17 10:52:21 +02:00
Florent Kermarrec
de4fc14cf9 software/bios/cmds/cmd_litsdcard: make sure all commands generate a report. 2020-09-17 10:41:49 +02:00
Florent Kermarrec
6c4abe2185 software/bios/cmds/cmd_liteeth: make sure all commands generate a report and improve it. 2020-09-17 09:10:58 +02:00
Florent Kermarrec
7d6818ab07 software/bios/command: avoid too much groups, reorganize a bit. 2020-09-17 09:07:36 +02:00
Florent Kermarrec
88ef2a330b software/bios/cmds/cmd_litedram: rename spdread command to sdram_spd. 2020-09-16 22:48:32 +02:00
Florent Kermarrec
3380de4adf software/bios/cmds/cmd_i2c: rename commands to i2c_xy. 2020-09-16 22:45:19 +02:00
Florent Kermarrec
79009f762d software/bios/cmds/cmd_spiflash: rename commands to flash_xy. 2020-09-16 22:44:47 +02:00
Florent Kermarrec
cb55d7119c software/bios/cmds/cmd_liteeth: rename commands to mdio_xy. 2020-09-16 22:39:56 +02:00
Florent Kermarrec
d5162a2a2b software/bios/cmds: use _handler suffix on all cmds functions. 2020-09-16 22:37:46 +02:00
Florent Kermarrec
d4018b7ccf software/bios/cmds/cmd_litesdcard: rename commands to sdcard_xy. 2020-09-16 22:32:27 +02:00
Florent Kermarrec
400bf13400 bios/cmds/cmd_mem: rename commands to mem_xy. 2020-09-16 22:25:33 +02:00
Florent Kermarrec
21cc7df2fa software/bios/cmds/cmd_mem: remove debug cmds that shouldn't have been merged. 2020-09-16 21:18:37 +02:00
Florent Kermarrec
74fb086322 software/liblitedram: rename functions/commands and expose mode register write function to user. 2020-09-16 20:01:39 +02:00
Florent Kermarrec
dc087f948a software/liblitedram/sdram: keep sdrwlon/sdrwloff private. 2020-09-16 11:56:39 +02:00
Florent Kermarrec
9c2975e8b4 software/liblitedram/sdram: remove low level manual controls of the DFI interface. 
This was too low level and unused.
 2020-09-16 11:22:15 +02:00
Florent Kermarrec
8a9d17c768 software/liblitedram/sdram.c: move sdrwl_delays definition to write_leveling section and add #ifdef on reinitialization. 2020-09-16 11:03:10 +02:00
Gabriel Somlo
9729d053eb software/memtest: use "unsigned long" to represent pointers 2020-09-15 14:46:18 -04:00
Gabriel Somlo
6c838cedcd libbase/sim_debug: wrap markers variables within appropriate #ifdef 2020-09-15 14:46:18 -04:00
Gabriel Somlo
e2719d4d71 fixup for e28e808c - don't define variable in .h file 2020-09-15 14:46:18 -04:00
Florent Kermarrec
a69273db50 boards/targets/arty: switch SDRAM to NETWORKING mode (interface_type no longer supported). 2020-09-15 19:59:20 +02:00
Florent Kermarrec
404104be21 software/liblitedram/sdram.c: increase ddrphy reset time. 2020-09-15 19:58:17 +02:00
Florent Kermarrec
cfe6f56572 software/liblitedram/sdram.c: improve reporting. 
- ident sub-reports.
- avoid displaying software/hardware swich if set to previous value.
 2020-09-15 19:41:20 +02:00
Florent Kermarrec
e63a40370e software/libbase/memtest: improve reporting. 
- indent sub-reports.
- report speed in MiB/s.
 2020-09-15 19:37:09 +02:00
Florent Kermarrec
e28e808c24 software/liblitedram: allow forced write leveling delays, improve delay printf when failing. 2020-09-15 19:34:09 +02:00
Florent Kermarrec
1d63d66a09 software/libbase/memtest: improve memtest_data progress. 
Add base/current tested address and current/total tested size.

ex:
Memtest at 0x40000000...
Write: 0x40000000-0x40200000 (2/2MiB)
Read:  0x40000000-0x40200000 (2/2MiB)
 2020-09-14 11:51:16 +02:00
Florent Kermarrec
b39fea4ecb software/liblitedram/write_level_scan: reset write delay even if not succeeding. 2020-09-07 18:53:31 +02:00
Florent Kermarrec
658f712001 software/liblitedram/write_level: add support for manual command delay. 
Required on some configurations where automatic cmd/clk scan still has troubles.
 2020-09-07 18:47:18 +02:00
enjoy-digital
5ee074f422
Merge pull request #642 from gsomlo/gls-sdcard-blk-vs-sec 
RFC: bios/sdcard: use (512 byte) blocks as the smallest addressable data unit
 2020-09-07 17:41:50 +02:00
Jędrzej Boczar
7c3fbf1d06 sim: improve tracing reset value and behaviour with sim_debug=False 2020-09-07 15:29:02 +02:00
Jędrzej Boczar
3fd567c4c9 sim: additional simulation tracing and debugging tools 2020-09-07 15:28:26 +02:00