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2722 commits

Author SHA1 Message Date
Konrad Beckmann
39d144626b Fix build issue where sdram_leveling is not found 
4f76656 rewrote how sdram_leveling() was called, leading
to linking problems for targets with sdram but with
write leveling disabled, e.g. ulx3s.
 2020-09-29 22:49:41 +02:00
Florent Kermarrec
a9234a8793 software/liblitedram: allow cmd_delay adjustment even when enforced by the phy. 2020-09-29 16:02:21 +02:00
Pepijn de Vos
eca5a25e27 add dummy attr_translate 2020-09-29 15:55:07 +02:00
Florent Kermarrec
4f76656018 software/liblitedram: simplify vtc/hardware/software controls. 
- move vtc control to sdram_software_control_on/off.
- remove sdram_calibration (duplicate of sdram_leveling).
- be sure to call sdram_software_control_on/off before all litedram bios commands.
 2020-09-29 15:40:26 +02:00
Pepijn de Vos
dd2b1f21f0 typo and dead code 2020-09-29 15:24:36 +02:00
Florent Kermarrec
e4555df095 tools/litex_server/pcie: enable pcie device if not already enabledd. 
Avoid having to do it manually or through a driver.
 2020-09-29 13:38:19 +02:00
Florent Kermarrec
bc5873f78c tools/litex_server/pcie: allow passing pcie bar as reported by lspci. 
ex:
$lspci
[...]
06:00.0 RF controller: Xilinx Corporation Device 7022 (rev 01)

sudo litex_server --pcie --pcie-bar=06:00.0
 2020-09-29 13:10:05 +02:00
Florent Kermarrec
6d07f01f5b tools/litex_client/RemoteClient: allow use without local csr.csv file. 
In some case, we just want to access MMAP manually without having the csr.csv file:
wb = RemoteClient()
wb.open()
wb.read(0x40000000)
wb.close()
 2020-09-29 13:01:44 +02:00
bunnie
7b42992383 add <memoryRegions> outer tag to series of <memoryRegion> for future proofing 2020-09-29 14:11:55 +08:00
bunnie
4a94bb78f6 add memory regions to soc.svd 
svd2rust does not recognize memory regions, but we'd like to
make an access crate for Rust that does.

This patch adds memory regions to soc.svd using the "vendorExtensions"
tag, as specified in https://www.keil.com/pack/doc/cmsis/SVD/html/svd_Format_pg.html

The vendorExtensions is added as a block after the Peripherals level, and has a format
like this:

```xml
        <memoryRegion>
            <name>SRAM</name>
            <baseAddress>0x10000000</baseAddress>
            <size>0x00020000</size>
        </memoryRegion>
        <memoryRegion>
            <name>VEXRISCV_DEBUG</name>
            <baseAddress>0xEFFF0000</baseAddress>
            <size>0x00000100</size>
        </memoryRegion>
        <memoryRegion>
            <name>CSR</name>
            <baseAddress>0xF0000000</baseAddress>
            <size>0x00040000</size>
        </memoryRegion>
```
 2020-09-29 01:30:09 +08:00
Pepijn de Vos
95564b7475 change name->devicename, working bios 2020-09-28 17:49:41 +02:00
Pepijn de Vos
c0fa4fd1f4 initial build support for Gowin 2020-09-28 13:12:07 +02:00
Florent Kermarrec
a1c023b900 software/bios/cmds/cmd_litedram: enable sdram_software_control before sdram_mode_register_write. 2020-09-24 14:58:42 +02:00
Florent Kermarrec
90a2b80b6a software/liblitedram/sdram_write_leveling_rst_cmd_delay: fix printf location (do it before taps is decremented). 2020-09-24 13:54:08 +02:00
Florent Kermarrec
7617a82fe6 targets/kcu105: create specific cd_eth for ethernet. 2020-09-24 10:27:48 +02:00
Florent Kermarrec
a3c616028e software/liblitedram/sdram: fix cmd_delays -> dat_delays. 2020-09-23 19:43:28 +02:00
Gabriel Somlo
8e7596d330 liblitesdcard/sdcard.c: ensure effective sdcard clock is <= requested 
With the way the clock divider is currently calculated, it is
possible for the effective sdcard clock to end up *higher* than
the requested `clk_freq` value.

Calculate the divider starting with the `CONFIG_CLOCK_FREQUENCY/clk_freq`
ratio which is then rounded up to the nearest power-of-two, ensuring
that the resulting, effective clock frequency is <= to the requested
frequency.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-09-22 15:15:50 -04:00
Florent Kermarrec
ac32b92e9f targets/kcu105: add etherbone. 2020-09-22 18:31:06 +02:00
Florent Kermarrec
a601415bf0 software/liblitedram: add functions/commands to reset and force cmd/dat write leveling delays. 
Useful to investigate/speed-up new board support.
 2020-09-21 19:53:34 +02:00
Florent Kermarrec
a39660fa99 software/liblitedram/sdram.c: fix typo. 2020-09-17 18:19:12 +02:00
Florent Kermarrec
a0d66dd60e software/liblitesdcard/sdcard: move busy_wait in sdcard_wait_cmd_done (fixes sdcardboot being stuck since code refactoring) and reduce busy_wait value. 2020-09-17 10:52:21 +02:00
Florent Kermarrec
de4fc14cf9 software/bios/cmds/cmd_litsdcard: make sure all commands generate a report. 2020-09-17 10:41:49 +02:00
Florent Kermarrec
6c4abe2185 software/bios/cmds/cmd_liteeth: make sure all commands generate a report and improve it. 2020-09-17 09:10:58 +02:00
Florent Kermarrec
7d6818ab07 software/bios/command: avoid too much groups, reorganize a bit. 2020-09-17 09:07:36 +02:00
Florent Kermarrec
88ef2a330b software/bios/cmds/cmd_litedram: rename spdread command to sdram_spd. 2020-09-16 22:48:32 +02:00
Florent Kermarrec
3380de4adf software/bios/cmds/cmd_i2c: rename commands to i2c_xy. 2020-09-16 22:45:19 +02:00
Florent Kermarrec
79009f762d software/bios/cmds/cmd_spiflash: rename commands to flash_xy. 2020-09-16 22:44:47 +02:00
Florent Kermarrec
cb55d7119c software/bios/cmds/cmd_liteeth: rename commands to mdio_xy. 2020-09-16 22:39:56 +02:00
Florent Kermarrec
d5162a2a2b software/bios/cmds: use _handler suffix on all cmds functions. 2020-09-16 22:37:46 +02:00
Florent Kermarrec
d4018b7ccf software/bios/cmds/cmd_litesdcard: rename commands to sdcard_xy. 2020-09-16 22:32:27 +02:00
Florent Kermarrec
400bf13400 bios/cmds/cmd_mem: rename commands to mem_xy. 2020-09-16 22:25:33 +02:00
Florent Kermarrec
21cc7df2fa software/bios/cmds/cmd_mem: remove debug cmds that shouldn't have been merged. 2020-09-16 21:18:37 +02:00
Florent Kermarrec
74fb086322 software/liblitedram: rename functions/commands and expose mode register write function to user. 2020-09-16 20:01:39 +02:00
Florent Kermarrec
dc087f948a software/liblitedram/sdram: keep sdrwlon/sdrwloff private. 2020-09-16 11:56:39 +02:00
Florent Kermarrec
9c2975e8b4 software/liblitedram/sdram: remove low level manual controls of the DFI interface. 
This was too low level and unused.
 2020-09-16 11:22:15 +02:00
Florent Kermarrec
8a9d17c768 software/liblitedram/sdram.c: move sdrwl_delays definition to write_leveling section and add #ifdef on reinitialization. 2020-09-16 11:03:10 +02:00
Gabriel Somlo
9729d053eb software/memtest: use "unsigned long" to represent pointers 2020-09-15 14:46:18 -04:00
Gabriel Somlo
6c838cedcd libbase/sim_debug: wrap markers variables within appropriate #ifdef 2020-09-15 14:46:18 -04:00
Gabriel Somlo
e2719d4d71 fixup for e28e808c - don't define variable in .h file 2020-09-15 14:46:18 -04:00
Florent Kermarrec
a69273db50 boards/targets/arty: switch SDRAM to NETWORKING mode (interface_type no longer supported). 2020-09-15 19:59:20 +02:00
Florent Kermarrec
404104be21 software/liblitedram/sdram.c: increase ddrphy reset time. 2020-09-15 19:58:17 +02:00
Florent Kermarrec
cfe6f56572 software/liblitedram/sdram.c: improve reporting. 
- ident sub-reports.
- avoid displaying software/hardware swich if set to previous value.
 2020-09-15 19:41:20 +02:00
Florent Kermarrec
e63a40370e software/libbase/memtest: improve reporting. 
- indent sub-reports.
- report speed in MiB/s.
 2020-09-15 19:37:09 +02:00
Florent Kermarrec
e28e808c24 software/liblitedram: allow forced write leveling delays, improve delay printf when failing. 2020-09-15 19:34:09 +02:00
Florent Kermarrec
1d63d66a09 software/libbase/memtest: improve memtest_data progress. 
Add base/current tested address and current/total tested size.

ex:
Memtest at 0x40000000...
Write: 0x40000000-0x40200000 (2/2MiB)
Read:  0x40000000-0x40200000 (2/2MiB)
 2020-09-14 11:51:16 +02:00
Florent Kermarrec
b39fea4ecb software/liblitedram/write_level_scan: reset write delay even if not succeeding. 2020-09-07 18:53:31 +02:00
Florent Kermarrec
658f712001 software/liblitedram/write_level: add support for manual command delay. 
Required on some configurations where automatic cmd/clk scan still has troubles.
 2020-09-07 18:47:18 +02:00
enjoy-digital
5ee074f422
Merge pull request #642 from gsomlo/gls-sdcard-blk-vs-sec 
RFC: bios/sdcard: use (512 byte) blocks as the smallest addressable data unit
 2020-09-07 17:41:50 +02:00
Jędrzej Boczar
7c3fbf1d06 sim: improve tracing reset value and behaviour with sim_debug=False 2020-09-07 15:29:02 +02:00
Jędrzej Boczar
3fd567c4c9 sim: additional simulation tracing and debugging tools 2020-09-07 15:28:26 +02:00
Florent Kermarrec
c247814ed4 software/liblitedram/sdram.c: add ifdef on MPR functions. 2020-09-05 11:37:07 +02:00
Florent Kermarrec
f7b6dd05ae cores/clock: add initial Xilinx Ultrascale Plus PLL/MMCM/IDELAYCTRL support. 2020-09-03 18:58:10 +02:00
Florent Kermarrec
6d8a367abe software/liblitedram: add separators, expose read_level. 2020-09-03 17:47:32 +02:00
Florent Kermarrec
ae152e28a7 software/liblitedram: add sdrmpr functions. 2020-09-03 15:25:04 +02:00
Florent Kermarrec
3e083958b0 software/liblitedram: move calibration to sdrcal function. 2020-09-03 14:55:37 +02:00
Florent Kermarrec
31afe55821 tools/litex_sim: avoid build/run duplication. 2020-09-03 09:21:37 +02:00
Florent Kermarrec
e8f21cd958 build/sim/verilator: cleanup SimVerilatorToolchain, return to initial path after build/run. 2020-09-03 09:21:14 +02:00
Gabriel Somlo
d86d20671e bios/sdcard: use (512 byte) blocks as the smallest addressable data unit 
In liblitesdcard/sdcard.c, replace s/sector/block/ as the 512 byte sized
unit of data transfer to/from the sdcard.

In bios/cmds/cmd_litesdcard.c, do NOT multiply block numbers by 512,
allowing any "block" (a.k.a. "sector") on the sdcard to be addressed for
testing.

Before this patch, user-input "block numbers" were multiplied by 512 and
passed into sdcard_[read|write]() as "sector numbers", with the sdcard
logic internally treating these as 512-byte sized addressable units on
the card. This resulted in only every 512'th 512-byte sized "sector" being
accessible from the bios command line.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-09-02 12:07:38 -04:00
Florent Kermarrec
222e3f4003 tools/remote/comm_uart: fix offset on write bursts. 2020-09-02 17:23:56 +02:00
Florent Kermarrec
6250d4fa41 integration/builder: fix bios_option typo. 2020-09-01 15:39:43 +02:00
Florent Kermarrec
267f3e30df integration/soc/add_spi_flash: update to use new API. 2020-09-01 12:27:43 +02:00
enjoy-digital
ee6dd5cd20
Merge pull request #644 from Xiretza/sdram-csr-map 
integration/soc: use csr.add() instead of add_csr()
 2020-09-01 12:08:33 +02:00
Florent Kermarrec
2538b2c300 soc/cores/clock: add with_reset parameter to create_clkout on iCE40PLL/ECP5PLL (similar to others PLLs). 
Avoid instantiating the AsyncResetSynchronizer manually.
 2020-09-01 11:50:08 +02:00
Florent Kermarrec
f07efcb97f integration/builder: change bios_options to list and add assert for supported options. 2020-09-01 11:48:52 +02:00
Xiretza
05e8ecf2e2
integration/soc: use csr.add() instead of add_csr() 
add_csr() is defined by SoCCore, so won't work for any instances of
LiteXSoC that aren't also SoCCores. Also, use use_loc_if_exists=True
so SoCCore.csr_map can be used without double allocation errors.
 2020-08-31 19:09:49 +02:00
Florent Kermarrec
043cfc5df7 soc/interconnect/axi/AXIStreamInterface: manage user as param. 2020-08-31 09:59:05 +02:00
Greg Davill
632cfcc257 soc/cores/cpu/serv: fix crt0 .data initialize 2020-08-30 10:52:16 +09:30
Greg Davill
dcd99cc999 soc/cores/cpu/minerva: fix crt0 .data initialize 2020-08-30 10:52:04 +09:30
Florent Kermarrec
bda54b1177 software/liblitedram: reset ddrphy before initialization if rst CSR present (added on 7-series). 2020-08-28 17:59:24 +02:00
Florent Kermarrec
b44ca6d61a soc/core/uart: add fixed burst support to UARTBone. 
Allows speeding-up consecutives accesses on the same address. This is currently
used by LiteDRAM bench to speed-up the logging of the BIOS over the crossover UART,
but could be useful for other purposes.
 2020-08-28 03:49:50 +02:00
Florent Kermarrec
1fb48d308e soc/cores/uart: add clock domain support to UARTBone. 
In some cases, we want to run UARTBone in a specific clock domain. For example
in LiteDRAM bench, UARTBone is controlling the SoC and the main PLL generating
the  sys_clk is reconfigured dynamically, so we want to run UARTBone in a specific
(and fixed) clock domain.
 2020-08-28 03:49:45 +02:00
Florent Kermarrec
566fbd60c3 cores/uart: minor cleanups on RS232PHYRX/TX. 2020-08-28 03:49:38 +02:00
Florent Kermarrec
587e09e3d6 software/liblitesdcard: increase sdcard_wait_cmd_done/sdcard_wait_data_done busy_wait. 
Required after the command refactoring, will need to be adjusted.
 2020-08-27 12:52:11 +02:00
Florent Kermarrec
4025257d8d software/liblitesdcard/sdcard: cleanup, update copyrights. 
- improve indent.
- remove do/while in block functions (block's length/count only need to be configured once).
- update copyrights.
 2020-08-27 12:36:35 +02:00
Florent Kermarrec
334635a97f software/liblitesdcard: remove wait for DMA Reader to complete, fix ifdef on SDCARD_CMD23_SUPPORT. 
The FIFO after the DMA has been reduced and is no longer able to store an entire block, so the DMA will not complete
if write is not released.
 2020-08-26 12:47:50 +02:00
Florent Kermarrec
4ac0ed49e1 software/liblitesdcard/bios: add sdfreq command to configure SDCard clock frequency. 2020-08-26 12:43:09 +02:00
Florent Kermarrec
3897acb9e4 lattice/nx: update copyrights. 2020-08-24 22:32:49 +02:00
Florent Kermarrec
4364043b08 integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone). 2020-08-24 18:19:03 +02:00
Piense
885c339d97 soc/cores: add initial NX-LRAM support. 2020-08-24 16:24:34 +02:00
Piense
cf13833e3c cores/clock: add initial NX-OSCA support. 2020-08-24 16:23:27 +02:00
Piense
e441bd60fa build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). 2020-08-24 16:23:22 +02:00
enjoy-digital
8a44464a45
Merge pull request #640 from antmicro/mor1kx_dt 
litex_json2dts: Add support for mor1kx
 2020-08-24 14:26:11 +02:00
Florent Kermarrec
4f1c32abdc targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. 2020-08-24 09:30:38 +02:00
Florent Kermarrec
d16051ff90 boards/ulx3s: keep up to date with litex-boards. 2020-08-24 09:08:30 +02:00
Florent Kermarrec
d826c60658 soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. 2020-08-24 09:04:33 +02:00
Florent Kermarrec
9e37b16ec0 soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. 
Not yet used, but simplify SoC integration.
 2020-08-24 09:03:04 +02:00
Mateusz Holenko
4dab1eb0c8 litex_json2dts: Add support for mor1kx 2020-08-24 08:02:16 +02:00
Florent Kermarrec
42d8fc226a Merge branch 'master' of https://github.com/enjoy-digital/litex 2020-08-23 15:42:39 +02:00
Florent Kermarrec
b8371ef480 tools: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:37:16 +02:00
Florent Kermarrec
93d906f9d1 soc: add SPDX License identifier and specify file is part of LiteX. 2020-08-23 15:33:01 +02:00
Florent Kermarrec
e52ffd2da0 gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. 2020-08-23 15:19:46 +02:00
Florent Kermarrec
70610b2332 build: add SPDX License identifier and specify file is part of LiteX. 2020-08-23 15:14:45 +02:00
Florent Kermarrec
6ee882d1ec platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. 2020-08-23 15:08:15 +02:00
enjoy-digital
ee0e240242
Merge pull request #631 from gsomlo/gls-abc9-fixup 
build/lattice/trellis: make "-abc9" an optional argument
 2020-08-22 20:06:57 +02:00
Florent Kermarrec
9950e75654 build/io: fix InferedSDRIO (thanks @mtdudek). 2020-08-22 19:49:34 +02:00
enjoy-digital
bae871a884
Merge pull request #632 from gsomlo/gls-sdcard-refactor 
refactor sdcard (bios) software
 2020-08-22 19:44:59 +02:00
enjoy-digital
3206dba911
Merge pull request #636 from Xiretza/minerva-cli-filetype 
Fix call to generation of minerva output file
 2020-08-22 19:41:07 +02:00
enjoy-digital
8bc5dd7c8c
Merge pull request #635 from Xiretza/collections-abc-deprecation 
Fix DeprecationWarning for collections.abc
 2020-08-22 19:40:44 +02:00
enjoy-digital
7984436248
Merge pull request #634 from betrusted-io/spi_opi_timing_only 
add a pipe register to relax an async_default timing path
 2020-08-22 19:39:51 +02:00
Xiretza
e3bb3a9488
Fix call to generation of minerva output file 
With nmigen/nmigen#a7b8ced, cli.py no longer defaults to generating
verilog code, so -t/--type has to be specified explicitly.

$ pytest test/test_targets.py -k test_variants_minerva
[...]
cli.py: error: specify file type explicitly with -t
 2020-08-22 14:54:40 +02:00
Xiretza
fcc7058bfc
Fix DeprecationWarning for collections.abc 
DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collections.abc' is deprecated since Python 3.3, and in 3.9 it will stop working
 2020-08-22 13:39:30 +02:00
bunnie
d783e86ff6 add a pipe register to relax an async_default timing path 
there is an async reset signal going to a FIFO
that can't be false_path'd because its timing is important
to making sure that the burst FIFO is reset to zero when
a miss happens in the burst cache. Unfortunately as designs
get full, the routability of this signal becomes difficult
and drives up the compile time and reduces quality of results.

There is enough time in the design to insert a single pipe stage
to alleviate the timing somewhat. This commit adds that register.
 2020-08-20 04:14:10 +08:00
Gabriel Somlo
e0b2b8153f liblitesdcard/sdcard: read sdcard response only when needed 
Instead of reading the 128 byte sdcard response after each operation,
read it only during debugging and/or when it's necessary (to retrieve
the relative card address, rca).

We no longer need a global sdcard_response array, and refactor the
various retrieval and reporting functions to contain a local buffer
for that purpose, only if/when necessary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-17 18:45:24 -04:00
Gabriel Somlo
a47b2de5fe sdcard: refactor command functions 
Factor out common portion of command functions. Also use appropriate
unsigned int width (e.g., uint16_t) for arguments.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-17 18:45:24 -04:00
Gabriel Somlo
bfd6b3c3f4 liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) 2020-08-17 18:45:24 -04:00
Gabriel Somlo
37ebcd3be7 factor out busy_wait_us() 2020-08-17 18:45:24 -04:00
Gabriel Somlo
c4710b371a build/lattice/trellis: make "-abc9" an optional argument 
Fix up earlier commit (#6c298cb7) and make the '-abc9' optional
argument to yosys' synth_ecp5 actually optional (and off by default)
in LiteX's trellis build infrastructure.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-15 16:49:08 -04:00
Florent Kermarrec
35929c0f8a soc/integration/csr_bridge: use registered version only when SDRAM is present. 
Seems to be a good compromise for now.
 2020-08-14 15:29:49 +02:00
Florent Kermarrec
e4f5dd987e interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. 2020-08-14 00:47:05 +02:00
Florent Kermarrec
b344196aba build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). 
http://www.latticesemi.com/en/Support/AnswerDatabase/5/5/2/5522
 2020-08-14 00:10:56 +02:00
Dolu1990
f730f1d7ba
cores/cpu/vexriscv_smp fix argument parsing 2020-08-13 12:52:05 +02:00
Florent Kermarrec
0e480dd662 bios/main/sdram: fix speed reporting (Mbps/pin not MHz). 2020-08-11 22:13:14 +02:00
Gabriel Somlo
ba34c85284 cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address 
Make the DMA base address register 64-bit wide, to cover situations
in which the physical memory being accessed is above the 4GB limit
(e.g., on 64-bit systems with more than 4GB of provisioned physical
memory).

Also update DMA reader/writer setup call sites in the bios (currently
only used by litesdcard).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-10 14:09:25 -04:00
Florent Kermarrec
4cf28a0107 software/bios: display SDRAM databits and freq. 2020-08-07 19:49:02 +02:00
Florent Kermarrec
6f69679d21 cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. 
LiteX is creating the SoC.dma_bus just after the CPU is declared, so declaring it in add_memory_buses was preventing it.
It's also more coherent to move it to __init__ since not related to the memory_buses.
 2020-08-07 14:47:21 +02:00
Florent Kermarrec
b3531cd2a8 cores/cpu: add external cpu_type. 
Allows fully pluggable CPUs where cpu_type is set to "external" and cpu_cls provided externally.
 2020-08-07 11:16:00 +02:00
Florent Kermarrec
b9d3aab59d targets: use platform.request_all on LedChaser. 2020-08-06 20:02:17 +02:00
Florent Kermarrec
14c9166429 build/generic_platform: add request_all method. 2020-08-06 20:00:07 +02:00
Florent Kermarrec
57335b9971 cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. 
And avoid the try/except that can mask others errors.
 2020-08-06 19:44:46 +02:00
enjoy-digital
4867f2b324
Merge pull request #624 from trabucayre/emio_zynq 
soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode
 2020-08-06 19:34:03 +02:00
Florent Kermarrec
48d63f2362 build/generic_plaform: add loose parameter to return None when not available/existing. 
Similar to loose parameter already present on Platform.lookup_request.
 2020-08-06 19:33:04 +02:00
enjoy-digital
81df7b7036
Merge pull request #625 from scanakci/blackparrot_litex 
Blackparrot human name change (IMA), minor transducer fix
 2020-08-06 18:50:39 +02:00
Florent Kermarrec
188e6f573a integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. 
Similar in most of the cases but added restrictions.
 2020-08-06 18:23:04 +02:00
sadullah
2457859b2d update BlackParrot transducer 2020-08-06 12:21:38 -04:00
sadullah
d2dabcef9a Blackparrot human name update 2020-08-06 12:21:38 -04:00
Gwenhael Goavec-Merou
87c26a30fd soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode 2020-08-06 16:45:39 +02:00
Dolu1990
07a8e696ce cpu/vexriscv_smp Add --with-coherent-dma 2020-08-06 13:33:11 +02:00
Florent Kermarrec
9a4c5aa1ef integration/soc/add_sdram: update rules to connect main bus to dram. 
Requires connection when CPU does not have memory buses of when CPU has memory buses
but no DMA bus.
 2020-08-05 18:01:12 +02:00
Florent Kermarrec
a1644510bf cpu/vexriscv_smp: fix args_read. 2020-08-05 17:59:30 +02:00
Florent Kermarrec
896b68cd6b cpu/vexriscv_smp: cleanup, fix coherent_dma connection. 2020-08-05 17:25:13 +02:00
enjoy-digital
342f359e1c
Merge pull request #622 from antmicro/fix_connectors 
arty: Change USB-uart and I2S Pmod configuration
 2020-08-05 12:30:34 +02:00
Florent Kermarrec
3b293612a8 soc/interconnect/axi: minor cleanups. 2020-08-05 12:11:28 +02:00
Florent Kermarrec
303d6cca7e interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. 2020-08-05 12:11:12 +02:00
Pawel Sagan
de9ea19cc7 arty: Change USB-uart and I2S Pmod configuration 
This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board).
 2020-08-05 11:38:51 +02:00
Florent Kermarrec
00629c45b0 interconnect/csr: add CSR registers ordering support. 
The original CSR registers ordering (big: MSB on lower addresses) is not convenient
when the SoC is interfaced with a real OS (for example as a PCIe add-on board or
with a CPU running Linux).

With this, the original ordering is kept as default (big), but it can now be switched
to little to avoid software workarounds in drivers and should probably be in the future
the default for PCIe/Linux SoCs.
 2020-08-05 08:57:19 +02:00
Florent Kermarrec
ee7a7f4693 soc/interconnect/csr: improve ident. 2020-08-05 07:59:35 +02:00
Florent Kermarrec
b1008b0164 integration/soc: add expection on decoder when full address space is mapped. 2020-08-04 19:56:26 +02:00
Florent Kermarrec
b831dc8c55 wishbone: revert default adr_width to 30. 2020-08-04 19:55:46 +02:00
Florent Kermarrec
abc49964ea tools/litex_json2dts: add missing copyrights. 2020-08-04 16:38:02 +02:00
Florent Kermarrec
aed0dcee4c setup: add litex_json2dts to console_scripts. 2020-08-04 16:07:53 +02:00
enjoy-digital
b64209b38b
Merge pull request #620 from antmicro/add_litex_json2dts 
Add Linux DT generation script
 2020-08-04 16:04:57 +02:00
Florent Kermarrec
0ca99b798f build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. 2020-08-04 15:49:53 +02:00
Florent Kermarrec
696ea468b8 build/sim: use json_object_get_int64 instead of json_object_get_uint64. 
json_object_get_uint64 does not seem supported with old json-c versions.
 2020-08-04 15:49:26 +02:00
enjoy-digital
382c1a3a44
Merge pull request #619 from antmicro/jboc/sim-clocker 
Allow to define multiple simulation clocks
 2020-08-04 15:38:28 +02:00
Mateusz Holenko
fafa844aa7 json2dts: Add Linux DT generation script 2020-08-04 15:13:17 +02:00
Jędrzej Boczar
f778ff09dc build/sim: improve timebase calculation (strict checks) and update modules 2020-08-04 14:00:58 +02:00
Florent Kermarrec
e0f131a317 cores/uart: add txempty/rxfull CSRs. 
Useful in some use cases, like flushing tx.
 2020-08-04 13:50:46 +02:00
Florent Kermarrec
2a3e39b10e tools/litex_server: enable read_merger with CommUDP. 
Limited to 4 (current size of the buffer in liteeth.frontend.etherbone).
 2020-08-04 10:55:51 +02:00
Florent Kermarrec
a5d0a340c3 test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. 2020-08-04 09:39:23 +02:00
Gabriel Somlo
561331ed97 debug: make CI print offending values 2020-08-03 16:59:39 -04:00
Gabriel Somlo
df3428be07 liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz 
Rocket's DMA slave interface (and/or internal routing) currently
appears unable to route DMA writes from LiteSDCard at frequencies
above 25MHz (as tested on nexys4ddr, with Rocket, at 75MHz main
system clock frequency).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
2d9dc8f939 cores/cpu/rocket: expose slave port for DMA 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
d8161e5a86 integration/soc: make DMA slave region cover (at least) the lower 4GB 
Assuming we currently support a 32-bit (4GB) physical address space,
ensure that the dma_bus slave covers the entire range, covering any
possible layout of the LiteX SoC memory map (e.g., rocket has MMIO
in a wide range of registers located below 2GB, and DRAM starting at
the 2GB mark, needing DMA accesses to be routed appropriately for the
entire 4GB physical address range).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-08-03 16:14:11 -04:00
Gabriel Somlo
70eae5cbf9 interconnect/wishbone: increase WB address width to 31 
This is needed to support memory regions up to 4GB in size (currently
limited to 2GB, or 0x8000_0000).

FIXME: CI complains about assertions re. axi_lite.address_width in
       relationship to len(wishbone.adr) and wishbone_adr_shift, which
       seems to be a problem on the 32bit (vexriscv?) CPU used for CI,
       but seems to work fine on Rocket.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

foo
 2020-08-03 16:11:26 -04:00
Gabriel Somlo
b8c9da81ea soc/interconnect/axi: add Wishbone2AXI converter 2020-08-03 12:50:00 -04:00
Florent Kermarrec
2ec4604c41 cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. 2020-08-03 18:47:17 +02:00
Jędrzej Boczar
c1ae7e596c build/sim: allow for arbitrary clocks generation using clockers 2020-08-03 17:06:38 +02:00
Jędrzej Boczar
38054874ac build/sim: use a real timebase in the simulation 2020-08-03 15:21:24 +02:00
enjoy-digital
5e53e5d73a
Merge pull request #615 from pepijndevos/openfpgaloader 
Add openFPGALoader programmer
 2020-08-03 14:01:50 +02:00
Pepijn de Vos
79ca4d9640 remove debugging 2020-08-01 11:07:04 +02:00
Pepijn de Vos
f6e20700d4 add openFPGAloader programmer 2020-08-01 11:05:09 +02:00
Florent Kermarrec
eab0726cc8 cpu/vexriscv/core: use variant name as human_name. 
Allow it to be shown in the BIOS and help support.
 2020-07-31 08:59:53 +02:00
Florent Kermarrec
e0a763e534 cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. 2020-07-31 08:58:30 +02:00
Florent Kermarrec
3ff1bcaf05 cpu/zynq7000: set csr map to 0x00000000. 2020-07-30 21:37:25 +02:00
enjoy-digital
c0253e3f77
Merge pull request #611 from antmicro/jboc/axi-lite 
soc/interconnect/axi: add AXILite -> AXI converter
 2020-07-30 14:22:21 +02:00
Florent Kermarrec
cc8440549f tools/litex_server/read_merger: review/simplify a bit. 2020-07-30 13:58:40 +02:00
enjoy-digital
4f382ccf55
Merge pull request #605 from cklarhorst/feature-uart-read-merger 
Merge sequential reads for the UART litex_server backend
 2020-07-30 13:56:48 +02:00
Jędrzej Boczar
e78d950a31 soc/interconnect/axi: add AXILite -> AXI converter 2020-07-30 13:50:34 +02:00
Florent Kermarrec
a942e358b9 cpu/blackparrot: minor cleanups, add sim variant (since use different flist). 2020-07-30 12:10:32 +02:00
Dolu1990
023ab15ec1 soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth 2020-07-29 12:40:16 +02:00
Dolu1990
e5cd5d5466 Merge branch 'master' into vexriscv_smp 2020-07-29 11:14:09 +02:00
Florent Kermarrec
1938ce363d integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. 
This is useful for CPUs elaborated at buildtime to use sdram's native data width on the CPU memory ports.
 2020-07-29 11:10:05 +02:00
Florent Kermarrec
6576416b8e cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. 
Useful for current tests with LiteSDCard using DMA and that requires the DMA to be connnected to
the DMA bus of Rocket when the direct memory bus is used.
 2020-07-29 09:35:15 +02:00
Dolu1990
789a70e7c8 Merge branch 'master' into vexriscv_smp 2020-07-28 19:11:54 +02:00
Dolu1990
d284dfbea9 soc/cores/cpu/vexriscv_smp config update 2020-07-28 19:07:02 +02:00
Florent Kermarrec
fe38e12b21 cpu/vexriscv_smp: move litedram import, remove os.path import. 2020-07-28 18:10:32 +02:00
Dolu1990
aa57c7a25e soc/cores/cpu/vexriscv_smp integration 2020-07-28 16:20:16 +02:00
Florent Kermarrec
f87513ab92 liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. 2020-07-28 14:36:49 +02:00
Florent Kermarrec
9518ccf453 integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). 2020-07-27 19:57:29 +02:00
Florent Kermarrec
9e07623b61 integration/soc: fix dma_bus typo. 2020-07-27 11:06:09 +02:00
Christian Klarhorst
2034c563b0 Merge sequential reads for the UART litex_server backend 
The UART backend writes [read identifier, num_reads, addr] for
every read request.
Etherbone packets are able to include multiple read requests.
Therefore, it is beneficial to merge sequential read requests to reduce writes
(and possible latency overhead).

Benchmark:
A typical litescope fetch script with the following
signals [ddrphy.dfi,cpu.ibus.cyc,cpu.ibus.stb] results in 1 read for the
data_valid register and 24 sequential reads for the scope data per timestamp.
Fetching data for a capture length of 512 over a 921600 baud UART (arty board)
took:
205s (current master branch)
 18s (with this merge function)

The proposed merger only merges read requests from one etherbone packet
at a time and doesn't change the read order.
 2020-07-26 13:19:32 +02:00
Florent Kermarrec
1fdffdfd6b targets: keep in sync with litex-boards. 2020-07-24 16:34:17 +02:00
enjoy-digital
8a0684b15e
Merge pull request #604 from antmicro/jboc/axi-lite 
Improve AXI Lite data width converters
 2020-07-24 14:54:11 +02:00
Jędrzej Boczar
879e6ffe73 soc/interconnect/axi: add basic AXI Lite up-converter 2020-07-24 13:47:18 +02:00
Sean Cross
dd366467ed litex: add sphinx_extra_config to generate_docs() 
This allows us to append additional strings to the sphinx `conf.py`.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-07-24 16:01:54 +08:00
Jędrzej Boczar
32160e615f soc/interconnect/axi: separate AXI Lite converter channels 2020-07-24 09:25:57 +02:00
Florent Kermarrec
041c7527ce core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. 
This is the logical continuation of the recent change to avoid specific SoC classes.
A Zynq FPGA can be used with or without the PS7. When used without the PS7, a softcore CPU
can be used as with others FPGAs. When using the PS7, the softcore is replaced with the PS7
and connected to the SoC through one of the AXI GP interface.

An example is available on litex-boards.
 2020-07-23 17:40:46 +02:00
Florent Kermarrec
8bdf6941a3 liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). 2020-07-22 23:15:36 +02:00
enjoy-digital
99e88dfc0b
Merge pull request #600 from antmicro/jboc/axi-lite 
Implement AXI Lite interconnect
 2020-07-22 23:03:07 +02:00
Florent Kermarrec
d38048baac soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). 
When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.

This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.
 2020-07-22 18:44:37 +02:00
Jędrzej Boczar
367eb12240 soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
706bc25dc1 soc/integration: add bus standard parser arguments 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
32d9e212c5 soc/interconnect/axi: improve Timeout module and test it with shared interconnect 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
2cab7fbf0f test/axi: add shared AXI Lite interconnect tests 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
3a08b21d44 soc/interconnect/axi: implement AXI Lite decoder 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
214cfdcaeb soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to 2020-07-22 17:16:33 +02:00
Jędrzej Boczar
a8a583d6b4 socinterconnect/axi: interconnect shared sketch 2020-07-22 17:16:26 +02:00
Jędrzej Boczar
f47ccdae99 soc/interconnect/axi: point-to-point interconnect and timeout module with tests 2020-07-22 17:16:12 +02:00
Jędrzej Boczar
b4c1120e3d soc/integration: choose interconnect based on bus standard 2020-07-22 17:16:07 +02:00
Jędrzej Boczar
69d8dd788d soc/integration: add axi-lite standard to SoCBusHandler 2020-07-22 17:13:28 +02:00
enjoy-digital
2361abb12d
Merge pull request #599 from antmicro/gen-mmcm-pr 
litex-gen: add mmcm core
 2020-07-22 14:52:26 +02:00
Piotr Binkowski
66c5f37133 litex-gen: add mmcm core 2020-07-22 12:34:32 +02:00
Florent Kermarrec
6b72f52c5d boards: keep in sync with litex-boards. 2020-07-22 08:50:38 +02:00
Florent Kermarrec
1f27b7405e soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. 2020-07-21 19:54:42 +02:00
Florent Kermarrec
408d1a9f5d cpu/vexriscv/system.h: update flush_cpu_dcache. 2020-07-21 19:43:00 +02:00
Florent Kermarrec
47ce15b431 interconnect/wishbone: add minimal UpConverter. 2020-07-21 19:35:14 +02:00
enjoy-digital
9fc488bdf6
Merge pull request #597 from antmicro/jboc/litex-buildenv-add-adapter-fix 
Fix Vivado crash when using 1:1 wishbone.Converter
 2020-07-20 23:11:01 +02:00
enjoy-digital
b92519502a
Merge pull request #595 from betrusted-io/master 
wire up missing register bits.
 2020-07-20 22:47:16 +02:00
Ilia Sergachev
8656ea9b67 interconnect/csr_bus: fix paged access warning 2020-07-20 18:23:09 +02:00
Jędrzej Boczar
07bc589c41 fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed 
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a
and litex bumped to 4a18b828bc,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
 2020-07-20 15:26:21 +02:00
Florent Kermarrec
4a18b828bc software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. 2020-07-20 13:48:49 +02:00
Florent Kermarrec
100aa5a4ca soc/cores/spi/SPIMaster: rewrite/simplify. 
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
 2020-07-20 10:44:18 +02:00
bunnie
53a567daef wire up missing register bits. 
Not sure how they went missing...but just noticed them.
 2020-07-19 03:00:25 +08:00
Florent Kermarrec
63c19ff45f liblitesdcard/spisdcard: update comments. 2020-07-17 15:39:39 +02:00
Florent Kermarrec
1f34f6ef00 soc/cores/spi: make sure done and miso are synchronous. 2020-07-17 15:38:52 +02:00
Florent Kermarrec
754f140a9d spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. 2020-07-17 11:58:26 +02:00
Florent Kermarrec
8143f1a08b soc/cores/spi: make sure miso is stable during xfer. 2020-07-17 11:56:27 +02:00
Florent Kermarrec
ac35e158c1 bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. 
For example:
{
	"Image":  "0x40000000",
	"bootargs": {
		"r1":  "0x12345678",
	}
}

will copy Image to 0x40000000 and set r1 to 0x12345678.

By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
}

is equivalent to:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
	"bootargs": {
		"r1":   "0x00000000",
		"r2":   "0x00000000",
		"r3":   "0x00000000",
		"addr": "0x00000000",
	}
}
 2020-07-16 18:12:11 +02:00
enjoy-digital
ee4b1d81a7
Merge pull request #594 from antmicro/jboc/axi-lite 
Add AXILiteDownConverter
 2020-07-16 17:56:33 +02:00
Jędrzej Boczar
229da572ff soc/interconnect/axi: propagate response errors in AXILiteDownConverter 2020-07-16 17:16:35 +02:00
Jędrzej Boczar
93bcc94b53 soc/interconnect/axi: implement AXILite down-converter 2020-07-16 17:02:49 +02:00
enjoy-digital
21c48eed76
Merge pull request #593 from antmicro/jboc/axi-lite 
Add AXILite components: AXILiteSRAM and AXILite2CSR
 2020-07-16 11:56:57 +02:00
Jędrzej Boczar
0be607dad9 soc/integration: revert bus argument for add_ram/add_rom 2020-07-16 10:26:12 +02:00
Jędrzej Boczar
2700ec3ce5 soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() 2020-07-15 15:59:16 +02:00
Jędrzej Boczar
f3072d4984 soc/interconnect/axi: add connect methods for convenience 2020-07-15 15:48:40 +02:00
Jędrzej Boczar
78a631f392 test/axi: add AXILite2CSR and AXILiteSRAM tests 2020-07-15 12:40:39 +02:00
Jędrzej Boczar
a5be2cd257 soc/interconnect/axi: improve SRAM/CSR access speed 2020-07-15 11:44:14 +02:00
Alessandro Comodi
3f7568de09 symbiflow: changed toolchain command names in Makefile 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-07-15 11:31:06 +02:00
Jędrzej Boczar
d8a242d86f soc/interconnect: add AXILite SRAM 2020-07-15 10:58:34 +02:00
Jędrzej Boczar
b692b2a3f1 soc/interconnect: add AXILite2CSR bridge 2020-07-15 10:36:34 +02:00
Jędrzej Boczar
35149c4e80 soc/integration: update add_adapter to convert between AXILite/Wishbone 2020-07-14 16:31:46 +02:00
Florent Kermarrec
6671eb6218 build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. 
Using fast-read as default prevent loading the .bit via JTAG (see #589).
 2020-07-13 11:55:03 +02:00
Florent Kermarrec
ae3c78f6d1 build/lattice/trellis: fix spimode typo. 2020-07-11 21:30:19 +02:00
Owen Kirby
0aec5b0f8c trellis: Add option to select SPI mode. 
This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.
 2020-07-11 11:48:10 -07:00
enjoy-digital
e76464167b
Merge pull request #587 from antmicro/mor1x_ror_instruction 
mor1kx: Do not generate the ror instruction
 2020-07-10 11:21:13 +02:00
Florent Kermarrec
468db3cf08 integration/soc/sdcard: add mode parameter to enable read only, write only or read+write modes. 2020-07-10 11:18:22 +02:00
Mateusz Holenko
b8d900862c mor1kx: Do not generate the ror instruction 
The mor1kx core does not support `l.ror` instruction
by default, but gcc/clang flags allowed the
compiler to generate it.
 2020-07-10 11:07:12 +02:00
Florent Kermarrec
b7e4507686 core/cpu/CPUNone: set endianness to little. 2020-07-10 10:42:00 +02:00
Filipe Laíns
235e8cf62b
cpu: add a few missing GCC toolchains 
This names are used by Arch Linux for eg.

Signed-off-by: Filipe Laíns <lains@archlinux.org>
 2020-07-09 15:58:33 +01:00
Florent Kermarrec
5ebdfd9307 liblitesdcard/sdcard: clamp divider value. 2020-07-09 13:09:36 +02:00
enjoy-digital
23085cffea
Merge pull request #584 from ozbenh/memtest 
Memtest/memspeed improvements
 2020-07-09 12:54:42 +02:00
Florent Kermarrec
5c332e4b58 cores/dma: add stream.last support on WishboneDMAReader. 2020-07-09 12:18:09 +02:00
Benjamin Herrenschmidt
83d24d087d memspeed: Write a fixed value 
Otherwise we have at least an extra addition in the loop
which squews the result compared to the read loop.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 17:13:37 +10:00
Florent Kermarrec
146ead4c4c buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation. 
Just create a local clk_domain from clk signal.
 2020-07-08 08:33:52 +02:00
Florent Kermarrec
b54b3b3362 interconnect/avalon: minor cleanup, remove max on SyncFIFO depth. 2020-07-08 07:53:42 +02:00
Benjamin Herrenschmidt
c0b948d4f9 memtest: Fix memspeed access size 
The move to libbase reverted the type of the pointer
from long to int.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 13:21:45 +10:00
Benjamin Herrenschmidt
798b3d7ba4 memtest: Fix integer size/type printf errors 
In a couple of places, memtest uses %x to print a pointer which
is illegal (and could be problematic on 64-bit). Use %p instead.

Additionally, use %ld when printing longs

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 13:17:48 +10:00
Florent Kermarrec
8af4e05c7f software/litesdcard: use new clocking and use slow clock during initialization. 2020-07-07 19:59:50 +02:00
Florent Kermarrec
52f36b1257 integration/soc/sdcard: cleanup emulator integration, fix sim. 2020-07-07 15:05:07 +02:00
Florent Kermarrec
7602977c16 integration/soc: move pads.rst control to PHY. 2020-07-07 14:58:06 +02:00