520c17e96d
soc_core: Add option to override CSR base
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When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.
However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.
This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
ecbd40284a
soc: Don't update CSR alignment when there is no CPU
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The alignment specified by the standalone core config should
be honored.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
f28f247130
soc: Don't create a wishbone slave to LiteDRAM with no CPU
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When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
33e202edd4
Bring into line with master
2020-05-12 12:28:09 +01:00
dcc881db92
soc: Don't create a share intercon with only one master and one slave
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This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
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Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
d2c9d38567
Merge pull request #508 from antmicro/update_litesdcard
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Update Litex bios to handle updated litesdcard.
2020-05-12 11:38:09 +02:00
dc1d452008
Addition of boot address parameter for trellis builds
2020-05-12 09:41:37 +01:00
0db3506997
Update Litex bios to handle updated litesdcard.
2020-05-12 10:07:16 +02:00
aed1d514ab
Update README.md and core.py for BlackParrot
2020-05-12 03:06:38 -04:00
5e4a436089
Vivado Command Update for Systemverilog
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Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
3ce9010083
Merge pull request #505 from DurandA/patch-3
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Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
e2176cefc2
soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters.
2020-05-11 22:39:17 +02:00
2c40967b5a
Enable 1x mode on SPI flash
2020-05-11 22:12:40 +02:00
1e610600f6
build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends.
2020-05-11 10:52:39 +02:00
ebcf67c10f
Merge pull request #502 from shuffle2/master
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diamond: project generation improvements
2020-05-11 09:55:52 +02:00
80f5327e3d
Merge pull request #490 from daveshah1/rdimm_bside_init
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Add RDIMM side-B inversion support
2020-05-11 09:42:55 +02:00
13db89ebd2
Merge branch 'master' into rdimm_bside_init
2020-05-11 09:42:35 +02:00
c9e36d7fdd
lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args.
2020-05-11 09:33:26 +02:00
ea7fe383a3
lattice/trellis: simplify seed support and add it to trellis_args.
2020-05-11 09:26:12 +02:00
5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
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Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-05-11 09:13:26 +02:00
5987ddb454
Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv
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Added `imac` config for CPUs …
2020-05-11 08:58:28 +02:00
c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv
2020-05-11 08:58:20 +02:00
59d88a880c
integration/soc/add_adapter: rename is_master to direction.
2020-05-11 08:47:50 +02:00
57390666d8
Merge pull request #504 from sergachev/master
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integration/soc: fix add_adapter for slaves
2020-05-11 08:34:03 +02:00
e4fa4bbcf7
integration/soc: fix add_adapter for slaves
2020-05-10 11:32:34 +02:00
2d70220b80
bios: Fix warning on 64-bit
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This fixes an incorrect printf format specifier
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00
ea232fc53a
BIOS boot firmware from SPI with address offset
2020-05-09 19:20:32 +02:00
eeee179dd8
diamond: close project when done
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Avoids ".recovery file is present" prompt.
2020-05-09 02:28:00 -07:00
9b782bd7da
diamond: clock constraint improvements
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Specify NET or PORT for freq constraints
Add equivalent timing closure check that diamond ui uses,
and default to asserting check has passed
2020-05-09 02:28:00 -07:00
fbbbdf03b5
core/led: simplify LedChaser (to have the same user interface than GPIOOut).
2020-05-08 22:13:47 +02:00
05869beb72
cores/led: add LedChaser (now that LiteX is running on FPGA mining boards let's use fancy led blinks :))
2020-05-08 13:18:12 +02:00
90c485fcc8
integration/soc: add clock_domain parameter to add_etherbone.
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To allow using a sys_clk < 125MHz with a 1Gbps link.
2020-05-08 13:16:26 +02:00
f1a50a2138
integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
2020-05-08 11:54:51 +02:00
79ee135f56
bios/sdram: fix lfsr typo.
2020-05-07 12:11:59 +02:00
162d32603d
Merge pull request #500 from mubes/fixups
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Fixups
2020-05-07 11:55:58 +02:00
d74f8fc93d
build/xilinx: add disable_constraints parameter to Platform.add_ip.
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When integrate .xci, we don't necessarily want to apply the default timing/loc
constrants generated by Vivado but our custom ones. Setting disable_constraints
to True allow disabling .xdc generated by the IP.
2020-05-07 11:34:26 +02:00
2a37b97d9f
Merge branch 'master' of https://github.com/enjoy-digital/litex into fixups
2020-05-07 09:36:41 +01:00
967e38bb57
Small fixups to address compiler warnings etc.
2020-05-07 09:26:46 +01:00
84841e1d58
bios/sdram: fix merge typo in lfsr (thanks Benjamin Herrenschmidt).
2020-05-07 08:21:57 +02:00
99c5b0fca1
bios/sdram: Use an LFSR to speed up pseudo-random number generation
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This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.
The LFSR implementation comes from microwatt's simple_random test
project.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:56:10 +02:00
34f268689a
Merge pull request #499 from DurandA/patch-2
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Add data dirs to manifest
2020-05-06 18:54:23 +02:00
8b9aa16d2e
boards/platforms: update xilinx programmers.
2020-05-06 16:16:41 +02:00
3c34039b73
build/xilinx/vivado: ensure Vivado process our .xdc early.
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When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.
Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
2020-05-06 13:13:01 +02:00
5e049d8966
Add data dirs to manifest
2020-05-05 22:15:24 +02:00
b057858071
gen/fhdl/verilog: explicitly define input/output/inout wires.
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When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
2020-05-05 16:58:33 +02:00
0aa3c339cc
targets/genesys2: set cmd_latency to 1.
2020-05-05 16:33:14 +02:00
95b57899cd
bios: remove usddrphy debug (we'll use a specific debug firmware to fix the usddrphy corner cases).
2020-05-05 16:27:21 +02:00
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
22bcbec03a
boards: keep in sync with LiteX-Boards, integrate improvements.
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- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
2020-05-05 15:27:56 +02:00
Benjamin Herrenschmidt
Dave Marples
enjoy-digital
Kamil Rakoczy
sadullah
Arnaud Durand
Ilia Sergachev
rprinz08
Shawn Hoffman