6a35337a09
gen/sim/vcd: allow continous update of vcd file and dynamic signals
...
With continous update, VCD header needs to be writen at the beginning of the simulation.
When a new signal is created, we rewrite the header and the content.
2016-05-28 10:25:48 +02:00
fa7ac6c9a2
build/sim/dut_tb: add bottom line on surface to show frame count
2016-05-23 10:20:05 +02:00
65f74959b3
gen/sim/core: add Display support
2016-05-18 15:47:10 +02:00
6fe3e1237d
gen/fhdl/structure: fix Display
2016-05-18 12:41:29 +02:00
36fd466324
build/sim/dut_tb: rename needs to wait
2016-05-12 15:39:51 +02:00
e890a566a9
buid/sim: add vga framebuffer with SDL
2016-05-04 20:17:02 +02:00
55c9c653e0
adapt to litedram changes
2016-05-04 00:59:02 +02:00
7a7b9420e6
soc/integration/soc_dram: sync with litedram
2016-05-03 19:44:33 +02:00
dca8b3c92e
boards/targets/sim: update litedram
2016-05-01 10:26:21 +02:00
69f0035315
gen/fhdl: add Display for debug in simulation
2016-04-29 23:03:43 +02:00
e79b2e3fef
boards/targets: SDRAM modules are now litedram.modules
2016-04-29 19:05:23 +02:00
3d71ba6e66
targets: remove sdram_controller_type parameter (minicon removed)
2016-04-29 17:51:16 +02:00
8c7332e75e
soc/integration/soc_sdram: use new LiteDRAM names
2016-04-29 17:40:55 +02:00
dc52d33fba
soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage)
2016-04-29 16:24:24 +02:00
44d766c09f
software/sdram: cleanup artix7 init
2016-04-29 15:55:10 +02:00
5fb0fe925e
setup.py: fix version (0.1)
2016-04-29 14:39:14 +02:00
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
42767286ca
gen/fhdl/verilog: add do in reserved_keywords
2016-04-27 17:43:25 +02:00
80d673e502
soc/integration/soc_sdram: always generate L2_SIZE constant
2016-04-27 12:34:18 +02:00
4e451a78d6
soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually)
2016-04-27 12:33:44 +02:00
ab8569916b
boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits
2016-04-26 23:29:35 +02:00
e6681bbb9c
soc/interconnect/wishbone: add FlipFlop (should be removed)
2016-04-25 19:14:20 +02:00
b6d8999471
platforms/arty: add missing address pins, was not going to work :(
2016-04-25 16:56:23 +02:00
f6e1c45d57
gen/genlib/record: fix connect
2016-04-21 19:05:01 +02:00
e80cfedd7f
gen/genlib/record: fix connect
2016-04-21 12:16:26 +02:00
9ae16c2f40
boards/platforms/nexys_video: use TDMS_33 on hdmi
2016-04-21 11:13:29 +02:00
3d98be0997
use new Record.connect omit parameter (replace leave_out)
2016-04-21 09:39:21 +02:00
c330e7be49
gen/genlib/record: rename leave_out by omit and add keep parameter to Record.connect
2016-04-21 09:39:12 +02:00
ee378b2557
boards/plaforms/nexys_video: fix hdmi_out pinout
2016-04-19 19:04:05 +02:00
849434c1bd
soc/software/bios: show cpu on first banner line
2016-04-19 09:19:37 +02:00
76bb0ef456
Merge pull request #2 from mithro/master
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More fixes.
2016-04-19 09:07:23 +02:00
1b9ab2f1fc
soc/integration/cpu_interface: fix clang detection
2016-04-19 08:06:56 +02:00
d9b598368f
Make verilator build output error messages.
2016-04-19 16:02:26 +10:00
8998ae5c92
bios: Print CPU architecture on boot.
2016-04-19 16:02:26 +10:00
e0e56e3655
Merge pull request #1 from mithro/master
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Bunch of small fixes
2016-04-19 07:49:24 +02:00
514496d744
libcompiler_rt: Fixing Makefile for CPU endianness.
2016-04-19 14:55:01 +10:00
5ba03160ed
soc/cores: fix spi
2016-04-19 06:49:23 +02:00
7b7f1dd68c
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-19 06:05:22 +02:00
e7f3c585b7
Allow using gcc for or1k.
...
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
* or1k continues to default to CLANG if environment is not net.
2016-04-19 14:03:24 +10:00
2f834d0aa2
bios: Use single characters for boot modes.
...
* The function keys never really worked properly.
* Also add commands for the ROM/Flash/etc.
2016-04-19 13:42:56 +10:00
429f533bd0
soc/cores/sdram/settings: simplify modules and fix timing margins computation
2016-04-18 18:22:53 +02:00
41f6408d56
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-15 08:09:42 +02:00
7b3699839e
build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint
2016-04-14 21:48:52 +02:00
3d222d9e63
soc/interconnect/dma_lasmi: change endpoint names
2016-04-13 18:28:52 +02:00
fcd8d792a1
Merge branch 'master' of https://github.com/enjoy-digital/litex
2016-04-13 01:19:21 +02:00
6e0045e6be
soc/integration/soc_sdram: allow passing controller settings in register_sdram
2016-04-12 20:16:47 +02:00
40eb779e67
software/include/base: fix system.h for or1k
2016-04-10 17:21:54 +02:00
238d69f186
software/common: use -std=gnu99 for GCC
2016-04-10 17:21:17 +02:00
b2eaf412c1
soc/interconnect/stream/PipelinedActor: add latency attribute
2016-04-07 12:10:32 +02:00
9fa9bdcf68
build/sim: adapt verilator simulation to new stream signals
2016-04-07 08:56:53 +02:00
Florent Kermarrec
Tim 'mithro' Ansell