f4d6ac8393
README: remove compiler-rt download instructions
2014-11-06 18:02:02 -08:00
09773df186
software: make compiler-rt a submodule
2014-11-06 18:00:28 -08:00
dff3a17711
mibuild/programmer: add migen folders to flash proxy search dirs
2014-11-05 23:23:22 +08:00
353e7fc13b
link: add SATALinkLayer skeleton (wip)
2014-11-04 22:55:31 +01:00
8f6354f2a3
link: improve crc_tb/ preamble_tb and increase length
2014-11-04 17:06:03 +01:00
c810009387
link: add Scrambler and testbench
2014-11-04 16:40:21 +01:00
8062298668
link: add CRC and testbench
2014-11-04 10:33:11 +01:00
7d15e91e26
vpi/ipc: fix decoding of index buffer
2014-11-04 16:57:34 +08:00
449daedab7
sata/link: add crc and scrambler C models from SATA specification
2014-11-03 18:11:14 +01:00
47b5ff5e33
move code and create a directory for each layer
2014-11-03 17:38:12 +01:00
ccc9a0d334
test/test_size: fix slice comparison
2014-11-03 12:08:43 +08:00
dcedc4e6a5
actorlib/structuring/Pipeline: make 'busy' a signal
2014-11-01 21:48:02 +08:00
33c3a927c2
actorlib/structuring: add Pipeline
...
Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
2014-11-01 21:47:00 +08:00
8db549a23d
actorlib/structuring: add Converter
...
Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
2014-11-01 21:43:52 +08:00
a7e4907724
Merge branch 'master' of github.com:m-labs/migen
2014-11-01 21:33:35 +08:00
bd1d456f5d
flow/actor, actorlib/structuring: add packet support
2014-11-01 21:22:46 +08:00
4d1b6da42f
bus/csr: add configurable address_width (needed more than 32 modules with CSR)
2014-11-01 21:22:11 +08:00
fcf2f7517c
crc: generate error asynchronously to avoid stalling the flow and simplify
2014-11-01 21:21:46 +08:00
648ab8fa7a
kc705: add Ethernet pins
2014-11-01 21:11:47 +08:00
c0c04a1878
xilinx_vivado: use .bat on Windows platforms (otherwise Vivado uses Unix scripts...)
2014-11-01 20:59:19 +08:00
51f699758c
xilinx_vivado: add hierarchical utilization report
2014-11-01 20:57:54 +08:00
a4782899f6
fhdl/verilog: fix tristate to instance connection
2014-10-29 18:18:17 +08:00
8c5c32751e
add input pipe stage option
2014-10-28 20:53:26 +01:00
25e0ccae9a
remove DRP ports (won't be used for now)
2014-10-28 11:33:15 +01:00
3f7406a937
various fixes and simplifications, SATA1 & SATA2 OK
2014-10-28 02:15:19 +01:00
286092b62e
Raise exception when not using correct boolean operators
2014-10-27 19:40:22 +08:00
e2cbb3a048
platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows)
2014-10-24 12:32:08 +02:00
86abb253c8
flow/actor/Endpoint: clean up __getattr__
2014-10-22 09:35:30 +08:00
37031e3a2f
DMAWriteController: fix Demultiplexer layout
2014-10-20 23:58:16 +08:00
8e4b89849c
use new direct access on endpoints
2014-10-20 23:13:37 +08:00
07c33279c2
use new direct access on endpoints
2014-10-20 23:12:16 +08:00
ff688fb2f9
_Endpoint: allow direct access of payload elements
2014-10-20 23:09:56 +08:00
34ed315a48
remove trailing whitespaces
2014-10-17 17:14:40 +08:00
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
d860813dec
use new direct access on endpoints
2014-10-16 17:57:30 +02:00
22507b117c
bank: add re to CSRStorage
...
being able to know when a register is updated is useful in many cases and avoid having to handle another register for that.
re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.
2014-10-16 17:43:41 +08:00
bbfce2b707
ctrl: drive txcomwake and not gtx.txcomwake in K7SATAPHYDeviceCtrl
2014-10-16 10:38:26 +02:00
9649b1497c
uart2wishbone: fix missing payload.d
2014-10-16 09:37:43 +02:00
2319ee0ab7
uart2wishbone: always use payload.d and not .d
2014-10-15 12:13:22 +02:00
027ddc65ca
fill __init__.py to simplify imports
2014-10-10 17:24:36 +02:00
bf95ea6c1c
mila: simplify usage
2014-10-10 16:17:12 +02:00
d0c9838dca
uart2wishbone: share UARTRX and UARTTX with MiSoC
2014-10-10 15:15:58 +02:00
20528c622a
mor1kx: sync
2014-10-10 15:38:05 +08:00
e53fb88b85
uart: minor cleanup and fix
2014-10-10 15:33:27 +08:00
5e5f436aa6
uart: split it and use dataflow
...
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
2014-10-10 15:24:47 +08:00
ba30a01830
mila: fixes when used without RLE
2014-10-06 12:30:06 +02:00
f72f11f7b4
mila: add clk_domain support
...
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.
future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
7043e6a5f3
mila: simplify export
2014-10-01 10:06:59 +02:00
b284819d18
revert simulation design and add wave
2014-09-30 11:10:15 +02:00
110580eb2e
add .payload. to Sink and Source to be compatible with upstream Migen
2014-09-30 11:03:36 +02:00
Sebastien Bourdeauducq
Florent Kermarrec
Yann Sionneau