35250f5b11
bios: add romboot
...
When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.
2015-07-14 18:01:44 +02:00
23541b5949
software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)
2015-07-04 21:04:23 +02:00
10eb07526d
bios: show memtest command in help
2015-07-02 17:20:06 +02:00
351e654e9d
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
2015-06-23 09:01:34 +02:00
f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
515398634f
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
2015-04-12 18:42:52 +02:00
f4c35e358e
software/bios/sdram: small clean up
2015-03-27 18:24:19 +01:00
6245dd7b6f
software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6
...
Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
2015-03-27 16:43:22 +01:00
f85a4f004b
software/bios/sdram: add random addressing to memtest
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testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
2015-03-27 15:49:16 +01:00
38d24b637e
software/bios/sdram: make seed_to_data static
2015-03-26 23:05:20 +01:00
e79a716425
software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
2015-03-26 22:16:31 +01:00
9bc71f374a
rename sdram mapping to main_ram
2015-03-21 21:01:46 +01:00
b75e4b237d
software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone.
...
we now need to add another random addressing test to avoid linear access on L2 cache
2015-03-21 20:29:15 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
8280acd3a7
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
2015-03-02 12:17:49 +01:00
0980becb56
sdram: improve memtest by adding 2 different writes/reads
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doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
36434b62f0
sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
2014-09-03 15:02:38 +08:00
2388bfabc3
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705.
2014-09-03 14:25:26 +08:00
6decb357f1
bios: add sdrrderr
2014-09-01 15:23:37 +08:00
57335bdf3f
bios: add DQ filtering to sdrrd, add sdrrdbuf command
2014-09-01 14:58:58 +08:00
0ebdf2be6d
bios/sdram: cleanup
2014-08-08 21:57:58 +08:00
b61dced909
bios/sdram: set ODT and RESET_N through DFII
2014-08-08 21:57:42 +08:00
293ac09673
sdramphy/bios: make sdrrd/sdrwr generic
2014-08-08 19:25:10 +08:00
dc2024f54d
bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM
2014-05-23 21:31:26 +02:00
398608e997
bios: fill delay slot in boot_helper
2014-05-14 16:08:25 +02:00
13e74b8b4f
software: factorize exception_handler
2014-05-14 15:01:38 +02:00
edf567a0cd
bios: fix boot for or1k
2014-05-14 15:01:02 +02:00
1c08aeb21c
Initial mor1kx (OpenRISC) support
...
Based on milkymist-ng-mor1kx by Stefan Kristiansson
2014-05-14 10:24:56 +02:00
87a8504304
Refactor CRC tools
2014-04-19 00:01:29 +02:00
93f02a8cf4
tools: replace mkmscimg with mkmscimg.py (mkmscimg.c was platform dependent)
2014-04-18 20:22:42 +02:00
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
fce46ac0ca
Simplify use of external targets/platforms/cores + add default platform in targets
2014-02-16 14:51:52 +01:00
a23dffd2c2
bios: update banner
2014-02-15 14:02:09 +01:00
f55943ae18
new action syntax for make.py + support xc3sprog
2014-02-15 14:01:50 +01:00
4ba796417d
software: do not attempt to build network/sdram drivers when cores are not present
2013-11-24 23:50:09 +01:00
d4063409e1
software/bios: infer flash start from linker
2013-11-24 23:45:03 +01:00
fca0b968e7
generate linker memory map, move all generated files into the same folder
2013-11-24 19:50:17 +01:00
c9e99dfca9
bios: flushl2 command
2013-11-16 16:27:34 +01:00
d7a4d8b66e
use git commit id as version
2013-11-09 16:38:44 +01:00
0b881d934f
rename milkymist-ng to MiSoC
2013-11-09 15:27:32 +01:00
25506c1ab5
software: share crt0
2013-07-11 18:36:26 +02:00
26ff6f2a9c
s6ddrphy: style and other minor fixes
2013-07-10 20:39:53 +02:00
60f1585fef
use Migen s6ddrphy, generate sdram init_sequence in cif.py
2013-07-10 19:56:09 +02:00
91d7b656a9
Switch to LASMI, bug pandemonium
2013-06-11 14:18:16 +02:00
45cfdf41fc
New simplified flash layout + build flashable images for SoC and videomixer
2013-06-01 17:20:40 +02:00
b6448ba5fc
bios: remove rescue
2013-05-28 16:15:30 +02:00
701aac2513
bios/linker.ld: flash -> rom
2013-05-28 16:15:17 +02:00
Florent Kermarrec
Yann Sionneau
Sebastien Bourdeauducq
Sebastien Bourdeauducq