Commit Graph

1329 Commits

Author SHA1 Message Date
Florent Kermarrec e133777450 targets/simple: add MiniSoC 2015-03-06 10:10:58 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec bee8ccf6c7 soc: enforce cpu_reset_address to 0 when with_rom is True 2015-03-06 08:21:16 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Sebastien Bourdeauducq 60e87f6e87 Merge branch 'master' of https://github.com/m-labs/misoc 2015-03-04 00:46:41 +00:00
Sebastien Bourdeauducq 073641faa1 litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
Florent Kermarrec 200791c81d uart: generate ack for rx (serialboot OK with sim) 2015-03-04 00:57:37 +01:00
Florent Kermarrec 7c058a52c9 com/spi: use .format in tb 2015-03-03 10:44:05 +01:00
Florent Kermarrec 0716dadaf2 targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works 2015-03-03 10:39:31 +01:00
Florent Kermarrec 1d4dc45436 LiteXXX cores: use format in prints 2015-03-03 10:29:28 +01:00
Florent Kermarrec f27e7a4b22 litesata: remove unneeded clock constraint 2015-03-03 10:24:05 +01:00
Florent Kermarrec 0bcd6daf63 soc: remove is_sim function 2015-03-03 10:15:11 +01:00
Florent Kermarrec 905be50451 sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy 2015-03-03 09:55:25 +01:00
Florent Kermarrec 9210272356 sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence 2015-03-03 09:23:21 +01:00
Florent Kermarrec 2f7206b386 sdram: revert use of scalar values for DFIInjector 2015-03-03 09:09:54 +01:00
Florent Kermarrec 9df60bf98e lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True) 2015-03-03 09:02:53 +01:00
Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
Sebastien Bourdeauducq 8e48502d03 spiflash: style 2015-03-03 00:54:30 +00:00
Sebastien Bourdeauducq 2513833a24 README: 80 columns 2015-03-03 00:17:34 +00:00
Sebastien Bourdeauducq 69a0c597ad make.py: use ternary getattr 2015-03-02 23:54:00 +00:00
Florent Kermarrec 410a162841 sdram: disable by default bandwidth_measurement on lasmicon 2015-03-02 19:53:16 +01:00
Florent Kermarrec ca42611b6b README: add Pipistrello 2015-03-02 19:18:46 +01:00
Florent Kermarrec 3449b7c933 update README 2015-03-02 18:41:03 +01:00
Florent Kermarrec 02ef1dc95a targets: fix mlabs_video FramebufferSoC 2015-03-02 18:38:43 +01:00
Florent Kermarrec 473997df26 cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
Florent Kermarrec 8280acd3a7 sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core 2015-03-02 12:17:49 +01:00
Florent Kermarrec 3465db25a7 soc/sdram: be more generic in naming 2015-03-02 11:55:28 +01:00
Florent Kermarrec 97331153e0 sdram: create core dir and move lasmicon/minicon in it 2015-03-02 11:38:22 +01:00
Florent Kermarrec de698c51e4 sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner) 2015-03-02 11:29:43 +01:00
Florent Kermarrec 6b24562eea sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest) 2015-03-02 10:59:43 +01:00
Florent Kermarrec 0980becb56 sdram: improve memtest by adding 2 different writes/reads
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
Florent Kermarrec 46020fd253 sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look) 2015-03-02 10:34:29 +01:00
Florent Kermarrec c0b38e4905 sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus 2015-03-02 09:18:32 +01:00
Florent Kermarrec 7300879b7f sdram: move dfii to phy 2015-03-02 09:08:28 +01:00
Florent Kermarrec 9ad05b21ca sdram: fix remaining data_valid in dma_lasmi 2015-03-02 09:05:18 +01:00
Florent Kermarrec 88e7fa21e4 sdram: create test dir and move lasmicon/minicon tests to it 2015-03-02 08:42:55 +01:00
Florent Kermarrec b305b7828a sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
Florent Kermarrec 6d83a112e6 lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks) 2015-03-01 22:04:27 +01:00
Florent Kermarrec f58394f6af soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :) 2015-03-01 18:25:47 +01:00
Florent Kermarrec 4f37d29d05 flash/spi: make bitbang optional (enabled by default) 2015-03-01 17:15:22 +01:00
Florent Kermarrec 096e95cb59 uart: use data instead of d on endpoint's layouts (coherency with others cores) 2015-03-01 16:56:48 +01:00
Florent Kermarrec 1e6d1deae8 uart: add sim phy 2015-03-01 16:52:50 +01:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec bd4d3cd73b uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator) 2015-03-01 12:14:34 +01:00
Florent Kermarrec 9e01bf5fdd litesata: create example design derived from SoC 2015-03-01 11:33:38 +01:00
Florent Kermarrec c21a7956c8 liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
Florent Kermarrec 67ca0da1d9 liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
Florent Kermarrec 7b464b2b1c litesata: create specialized kc705 platform to avoid duplicating things already in mibuild 2015-03-01 11:03:15 +01:00
Florent Kermarrec 32fce11edf litescope: avoid uart code duplication 2015-03-01 10:07:55 +01:00