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7920 Commits

Author SHA1 Message Date
Ilia Sergachev 0c57021c3c software: add minimal xilinx library makefile 2021-12-22 03:00:05 +01:00
Ilia Sergachev 6705972713 builder: enable bios compilation on zynq 2021-12-22 02:59:40 +01:00
Ilia Sergachev 76148c4930 zynq: add minimal software compilation support 2021-12-22 02:58:33 +01:00
Ilia Sergachev 4f39faf737 software/libc: enable compilation on arm 2021-12-22 02:57:52 +01:00
Ilia Sergachev 94f4dd78f2 zynq: update gcc triple, set fpu flags 2021-12-22 02:57:07 +01:00
Ilia Sergachev a07a4e0e86 zynq: cleanup 2021-12-22 02:56:46 +01:00
Ilia Sergachev 68e40dd330 zynq: remove broken unused method 2021-12-22 02:56:21 +01:00
Ilia Sergachev b7f787a461 software: disable exceptions on arm cpus (problems compiling) 2021-12-22 02:55:33 +01:00
Ilia Sergachev 5357d66c93 software/libc: fix missing return 2021-12-22 02:54:32 +01:00
Ilia Sergachev 4c20501218 software/libcompiler_rt: enable missing math operations on arm 2021-12-22 02:54:19 +01:00
Ilia Sergachev 490929ab65 software/libcompiler_rt: cleanup flags 2021-12-22 02:53:58 +01:00
Ilia Sergachev 893044275e software/libc: remove fexceptions flag already present in common.mak 2021-12-22 02:53:24 +01:00
Ilia Sergachev ab8c509396 argparse: deduplicate defaults in help messages 2021-12-22 02:45:58 +01:00
enjoy-digital d36e1b60bd
Merge pull request #1139 from tilk/jtagbone_typo 
Fix typo jtabone -> jtagbone
 2021-12-21 19:22:01 +01:00
Marek Materzok 92c8f7dc7c Fix typo jtabone -> jtagbone 2021-12-21 18:10:12 +01:00
enjoy-digital 72126f90a0
Merge pull request #1138 from fjullien/efinix_add_ifacewriter_mipi_clkin 
efinix: add gpio MIPI_CLKIN to ifacewriter
 2021-12-21 15:34:51 +01:00
enjoy-digital 1a9716048f
Merge pull request #1136 from antmicro/fix-regions-filter 
tools/litex_json2renode: Add more restrictions to memory regions filter
 2021-12-21 15:34:25 +01:00
Franck Jullien 2174a9219b efinix: add gpio MIPI_CLKIN to ifacewriter 2021-12-21 12:39:22 +01:00
enjoy-digital 55268af279
Merge pull request #1129 from gsomlo/gls-json2dts-update 
clock, mmc updates for json2dts_linux
 2021-12-20 21:27:06 +01:00
enjoy-digital 9e44e856cc
Merge pull request #1137 from trabucayre/zynq_tcl_preset 
zynq7000: add TCL preset support
 2021-12-20 21:25:40 +01:00
enjoy-digital 58f9bce567
Merge pull request #1135 from fjullien/bios_add_variable_size_mem_write 
bios: add write size option to cmd mem_write
 2021-12-20 21:23:16 +01:00
Gwenhael Goavec-Merou 14e0aeb92a zynq7000: add TCL preset support 2021-12-20 16:54:18 +01:00
Robert Szczepanski bf52f222af tools/litex_json2renode: Add more restrictions to memory regions filter 
Skip regions that have size==0 or if region is included in another region.
Abort script if region overlap on another region.

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
 2021-12-20 13:56:40 +01:00
Franck Jullien f4dab5adac bios: add write size option to cmd mem_write 2021-12-17 20:45:41 +01:00
enjoy-digital 321b91d551
Merge pull request #1134 from fjullien/efinix_titanium_support 
Efinix titanium support
 2021-12-17 15:55:08 +01:00
Franck Jullien ca67ed8c13 efinix: check SLEWRATE property when adding a 'normal' GPIO 2021-12-17 13:52:05 +01:00
Franck Jullien df20ea5aa8 efinix: when a GPIO block is added, also add pin properties 2021-12-17 13:52:05 +01:00
Franck Jullien df34b3ae6a efinix: supports for EfinixTristateImpl with nbits > 1 2021-12-17 13:51:56 +01:00
Florent Kermarrec a6ed4c5c09 cores/prbs: Change wrap parameter to with_errors_saturation (opposite) and disable saturation by default. 2021-12-14 09:41:17 +01:00
enjoy-digital fda682a4a6
Merge pull request #1132 from smunaut/prbs 
cores/prbs: Add a 'wrap' option to PRBSRX
 2021-12-14 08:17:08 +01:00
Sylvain Munaut 477e51849a cores/prbs: Add a 'wrap' option to PRBSRX 
If enabled, then the error count wraps around when it
reaches the limit of the 32b counter instead of saturating
to a max value.

Software can then detect the wrap and act accordingly.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-12-13 19:46:06 +01:00
Florent Kermarrec e50ff33c6e test/test_cpu: Disable Minerva test for now. 2021-12-13 16:51:23 +01:00
enjoy-digital cec83a5dd8
Merge pull request #1131 from fjullien/efinix_titanium_support 
Efinix titanium support
 2021-12-13 15:44:04 +01:00
Franck Jullien 40c001d522 check calculated PLL frequencies against user's values 2021-12-13 14:47:57 +01:00
Franck Jullien eafee9dac5 efinix: add Titanium PLL support 2021-12-13 14:47:49 +01:00
Franck Jullien 148d124d03 efinix: get family name from device name 2021-12-13 14:36:54 +01:00
Franck Jullien f37188c358 efinix: add more valid IOStandard 2021-12-13 14:34:08 +01:00
Franck Jullien 12e5443489 efinix: fix efxpt:single_conn parsing 
Sometimes instance can be this form:

<efxpt:single_conn ... instance="GPIOT_PN_16.lvttl1,...

This patch handle this case
 2021-12-13 14:31:34 +01:00
Florent Kermarrec 92f5a9f0e6 soc/cores/led/WS2812: Add Bus Mastering capability. 
Useful on small FPGAs to reduce resource usage: When enabling bus mastering,
the core is able to automatically read led values from the bus and can then
avoid the internal memory. This is particularly useful when reading values
from SPI Flash with a small "Player" core just updating the base address.
 2021-12-12 15:18:24 +01:00
enjoy-digital 649c45e962
Merge pull request #1128 from gregdavill/fatfs-alignment-fix 
software.fatfs: Align fatfs sector buffers
 2021-12-10 21:54:34 +01:00
enjoy-digital 65a8249f4b
Merge pull request #1130 from whitequark/master 
litex_setup: nMigen has been renamed to Amaranth HDL
 2021-12-10 21:43:04 +01:00
whitequark 9329d3f092 litex_setup: nMigen has been renamed to Amaranth HDL. 2021-12-10 17:41:30 +00:00
Gabriel Somlo d108d2ad3d tools/litex_json2dts_linux.py: update mmc node 
Add `reg-names` property, which facilitates cleaner probing
for the upstream Linux device driver. Also, add a reference
to the LiteX sys_clk, also for the benefit of the upstream
driver, which can't rely on the CPU frequency matching sys_clk.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-12-10 11:05:58 -05:00
Gabriel Somlo b4fb3ea981 tools/litex_json2dts_linux.py: update clock specification 
Remove `bus-frequency` property from `soc` node. Instead,
create a separate `clocks` section containing a node to
represent the LiteX sys_clk, which may be referenced from
other peripherals if needed.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-12-10 11:02:35 -05:00
Greg Davill 416886c723 software.fatfs: Align fatfs sector buffers 2021-12-10 17:27:26 +10:30
Florent Kermarrec 230ba5f7ba cpu/gowin_emcu: Minor cosmetic cleanups, add copyright. 2021-12-09 16:01:41 +01:00
enjoy-digital 7286f95f55
Merge pull request #1125 from fjullien/efinix_add_bank_voltage 
efinix: add io bank voltage configuration
 2021-12-09 14:26:33 +01:00
enjoy-digital 435e16c421
Merge pull request #1126 from sergachev/feature/gowin_emcu 
Add initial Gowin EMCU support
 2021-12-09 14:25:04 +01:00
Ilia Sergachev db83b38a2a cores/cpu: add initial Gowin EMCU support 2021-12-08 23:51:57 +01:00
Ilia Sergachev 18a1d74cf6 soc/interconnect: add basic ahb support 2021-12-08 23:08:45 +01:00