cbd621ef2c
software/stdlib: fix atoi
2013-05-31 14:44:52 +02:00
7c95d253d9
software/videomixer: improve phase calibration
2013-05-30 21:40:16 +02:00
30f5ef8895
software/videomixer: remove unneeded DCM resets
2013-05-30 21:39:56 +02:00
084aa64a2a
dvisampler/clocking: remove DCM_CLKGEN
2013-05-30 21:38:45 +02:00
6d71e09281
cif: move to milkymist folder
2013-05-30 21:38:21 +02:00
cebfe787db
genlib/misc: fix import
2013-05-30 18:46:52 +02:00
ebbd5ebcd2
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
2013-05-30 18:45:04 +02:00
f0b0942055
bitreverse: fhdl/tools -> genlib/misc
2013-05-30 18:44:37 +02:00
548f2685bb
platform/rhino: rename ismm data out signal to locked
2013-05-30 11:06:02 +02:00
b6448ba5fc
bios: remove rescue
2013-05-28 16:15:30 +02:00
701aac2513
bios/linker.ld: flash -> rom
2013-05-28 16:15:17 +02:00
fdb021c992
dvisampler: increase frequency of reports to avoid missing WER values
2013-05-28 16:15:00 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
fb3e61230b
Use new memory port API
2013-05-28 15:56:14 +02:00
759858f739
Use migen.fhdl.std
2013-05-26 18:07:26 +02:00
c13e573e9f
Require Python 3.3
2013-05-26 18:02:18 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
611c4192b1
Use migen.fhdl.std
2013-05-22 17:10:13 +02:00
5208baada8
bus/wishbone/SRAM: support init and read_only
2013-05-19 20:53:54 +02:00
7ada0159fd
bus/csr/SRAM: support init
2013-05-19 20:53:37 +02:00
e272e68fac
platforms/papilio_pro: swap tx/rx to be consistent with M1
2013-05-19 20:24:47 +02:00
3eb41f73e6
Simplify system ID
2013-05-19 19:44:00 +02:00
d487dc607f
software: add nofloat libbase for size-optimized binaries
2013-05-19 12:41:40 +02:00
fb6cd481f0
dvisampler: report the word error rate
2013-05-16 22:38:55 +02:00
45797f9132
framebuffer: saturate instead of overflow
2013-05-16 17:45:21 +02:00
a39bf8ca7b
software/videomixer: support additive blending (enable with SW1, status on LED)
2013-05-16 17:44:49 +02:00
ac64701e19
software/videomixer: better pot calibration
2013-05-16 17:43:56 +02:00
71cc2db867
Add GPIO buttons and LEDs
2013-05-16 17:43:20 +02:00
27accd72b5
setup.py: update required Python version
2013-05-16 15:24:11 +02:00
581cf5bcb8
timer: atomic reads
2013-05-13 17:18:30 +02:00
9f81afb844
software/videomixer: connect crossfade and blackout pots
2013-05-13 15:45:28 +02:00
32c478af16
top: integrate ADC for pots
2013-05-13 15:45:06 +02:00
fe64ade1ac
platforms/m1: add pots pins
2013-05-13 15:38:20 +02:00
6bf6477dbc
Merge pull request #1 from fallen/makefile-001
...
Some Makefile love
2013-05-13 00:38:26 -07:00
bb73558ccc
software/videomixer: framebuffer enable/disable
2013-05-12 21:46:16 +02:00
792b8fed1b
bus/asmi: port sharing support
2013-05-12 15:58:39 +02:00
534dec62eb
First video mixing working (hacky)
2013-05-12 15:58:08 +02:00
301008cd0c
Some Makefile love
2013-05-12 14:24:18 +02:00
f202946717
fhdl/tools/_TargetLister: do not include array keys in targets
2013-05-11 17:28:41 +02:00
e35315bb24
cleanup
2013-05-11 12:45:30 +02:00
0ec6a7eb4e
genlib/record: match_by_position -> connect_flat
2013-05-11 11:48:21 +02:00
8c335d66fd
framebuffer: fix alpha blending
2013-05-11 09:21:12 +02:00
e96b027dee
Framebuffer mixing
2013-05-10 21:03:55 +02:00
955a9733c8
Revert "genlib/record/connect: add match_by_position"
...
This reverts commit df1ed32765
2013-05-10 17:41:51 +02:00
3ab83fb693
framebuffer: reorganize in preparation for mixer
2013-05-09 19:23:22 +02:00
6f11ddb079
software/dvisampler: periodically reset PLL until locked + recalibrate IO every second
2013-05-09 14:11:08 +02:00
546aa76aef
software/dvimixer: support two channels
2013-05-09 13:41:21 +02:00
06064d33aa
dvisampler/dma: better 8:8:8 -> 10:10:10 conversion
2013-05-09 11:27:24 +02:00
c6d553e4e4
software/videomixer: interrupt-driven video passthrough
2013-05-09 10:52:43 +02:00
fe87221d2b
dvisampler/dma: reverse slot allocation order
2013-05-09 10:51:50 +02:00
Sebastien Bourdeauducq
Yann Sionneau