Sebastien Bourdeauducq
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f69674e89c
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interconnect: add bus/bank components from Migen
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2015-09-24 20:48:18 +08:00 |
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Sebastien Bourdeauducq
|
ecdc4101b4
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lasmicon: enable refresh at all times
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2015-09-24 16:01:08 +08:00 |
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Sebastien Bourdeauducq
|
9b08b037e4
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break down sdram, improve consistency of core names
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2015-09-24 15:59:55 +08:00 |
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Sebastien Bourdeauducq
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0f410e45f1
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cores directory
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2015-09-24 09:05:10 +08:00 |
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Sebastien Bourdeauducq
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83509163df
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reorganization WIP: flatten core structure (SDRAM still needs to be done)
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2015-09-24 00:18:27 +08:00 |
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Sebastien Bourdeauducq
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82236d9b40
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migen.fhdl.std -> migen
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2015-09-23 00:36:47 +08:00 |
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Sebastien Bourdeauducq
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bd74d39338
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misoclib -> misoc
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2015-09-23 00:35:02 +08:00 |