1e2ad2250d
compat/soc_core: Fix register_mem/rom missing imports.
2022-11-09 19:11:15 +01:00
7157b4c5e8
Merge pull request #1496 from MateuszKarlic/json2renode-update
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json2renode: Multicore configuration support
2022-11-09 15:52:31 +01:00
877dff8a09
soc/compat: Fix add_wb_slave compatibility that was no longer working correclty since finalization order changes.
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We should really remove this compatibility layer, but let's wait a bit to make
sure all designs are converted.
2022-11-09 15:40:09 +01:00
8a74eba4d5
software/liblitedram: scale up values when finding CMD delay
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The delay finding code is based on integers, and when divided by the
count, rounding error will be quite easy to happen.
Scale up all delay value by 256x to reduce rounding error.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-09 17:55:49 +08:00
a7a520695e
software/liblitedram: seek for consecutive delay range when centering
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On some boards, the working delay range found may be not so consecutive.
Considering this to be some inference, we should only count the biggest
consecutive delay range instead of just skip ahead for a fixed offset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-09 17:50:34 +08:00
4a740651f0
litex_sim: Simplify configuration by creating a temporary config_soc that is then used for the configuration.
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This avoid several workarounds for CPU endianness, Bus data-width, RAM boot offset.
2022-11-09 09:24:30 +01:00
89afed5970
litex_sim: Switch to new LiteXArgumentParser and let it handle verilator build args.
2022-11-09 08:45:48 +01:00
c39d35de83
build/sim/platform: Add fill_args/get_argdict methods.
2022-11-09 08:45:12 +01:00
a2aa891baa
build/paltform: Minor cleanup on supported_toolchains/toolchain_group.
2022-11-09 08:44:49 +01:00
a2b5bb0db2
litex_sim: Switch from self.submodules to self.
2022-11-09 08:21:53 +01:00
d5df6e23f4
Merge pull request #1490 from Icenowy/litex-sim-membase-hack
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tools/litex_sim: hack to allow memory base other than 0x40000000
2022-11-09 08:18:50 +01:00
cd90e2623a
json2renode: cpu: Overhaul generate_cpu
2022-11-08 15:32:09 +01:00
eccb26874e
json2renode: cpu: Extract minor common logic
2022-11-08 15:32:09 +01:00
97772eb4bd
json2renode: IRQ: Fallback to cpu0 if plic is unavailable
2022-11-08 15:32:09 +01:00
4c959740dd
json2renode: Use cpu_count as local variable
2022-11-08 15:32:09 +01:00
b4bddc68e7
json2renode: Add LiteX MMCM
2022-11-08 15:32:09 +01:00
65964692dd
json2renode: Add auto-align hint
2022-11-08 15:32:09 +01:00
8b9ca8e9e9
json2renode: Silence false warnings about unsupported peripherals
2022-11-08 15:32:09 +01:00
283a237876
json2renode: Fix registration of GPIO peripherals
2022-11-08 15:32:09 +01:00
a9caeda30e
json2renode: Fix typo
2022-11-08 15:32:09 +01:00
55dcee16c3
json2renode: Use spiflash->base instead of flash_boot_address
2022-11-08 15:32:09 +01:00
860ca8673e
json2renode: Use opensbi->base for bios binary
2022-11-08 15:32:09 +01:00
ca63d12509
json2renode: Add support for multicore builds
2022-11-08 15:32:09 +01:00
240b24b7ff
gen/fhdl/hierarchy: Use [] for BlackBoxes.
2022-11-08 15:08:12 +01:00
b32d694ae4
interconnect/axi: Do not expose dest on AXI-Full (Only present for on AXI-Stream).
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We are using AXI-Stream for AXI-Full channels, so do an exception for dest signal.
2022-11-08 14:52:05 +01:00
f617e823b9
Merge pull request #1495 from Icenowy/openc906-debug
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cpus/openc906: add debug variant like vexriscv
2022-11-08 14:01:40 +01:00
85273ffe99
cpu/openc906: add debug variant that connects CPU DM to main bus
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The OpenC906 CPU core contains a RISC-V debug spec 0.13 compliant DM
with APB as its interface.
Add a CPU variant "debug" that will connect that APB to the main bus for
debugging.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-08 09:24:47 +08:00
9493338c68
cpu/openc906: fix the semantics of self.reset
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LiteX defaults to active-high reset signals, but OpenC906 uses
active-low ones, and the self.reset signal of openc906 module is wrongly
wired that it will force the CPU to run instead of force it to reset
(because it is ORed and then feed to the active-low reset line).
Fix this by using AND and inverting self.reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-08 09:24:47 +08:00
ff3bd11de1
Merge pull request #1494 from trabucayre/parset_fix_target_group
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litex/build/parser: check if self._target_group is not None before calling add_argument
2022-11-07 21:03:37 +01:00
98912f45e0
litex/build/parser: check if self._target_group is not None before calling add_argument
2022-11-07 20:40:09 +01:00
3269d12a27
gen/fhdl/hierarchy: Use ** for BlackBox for black/white consoles.
2022-11-07 19:19:14 +01:00
f43b92103a
build/sim/core/Makefile: Add -Wno-COMBDLY and -Wno-CASEINCOMPLETE flags to disable more these warnings (thanks @suarezvictor).
2022-11-07 15:26:35 +01:00
3c52d440a6
build/parser: Fix CPU listing when invalid one is provided and simplify.
2022-11-07 13:34:09 +01:00
1ce3271efe
build/parser: Add LiteXSoCArgumentParser compatibility and switch to it in integration/soc.
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Move things a bit to add target_group only when platform is set and avoid recursive imports.
2022-11-07 13:16:24 +01:00
a2cb04b218
LICENSE: Update.
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- Update project description.
- Add plain text BSD 2-Clause License for Github detection.
- Add LiteX developers to copyrights (similar to README).
- Add "moral" conditions for use of the project.
2022-11-07 10:00:59 +01:00
9ccf08e22d
build/parser: Rename soc_core_argdict to soc_argdict.
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The next move was to avoid use of soc_core_argdict and prefer use of soc_argdict directly,
so rename method now to avoid use on soc_core_argdict on targets/designs.
2022-11-07 08:45:24 +01:00
2e46a81bf6
tools/litex_sim: hack to allow memory base other than 0x40000000
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The LiteX OpenC906 core currently uses 0x0 as the base of main memory.
Hack to allow this when preloading a binary in litex_sim by adding a
command line argument.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-07 11:48:15 +08:00
3b4bb083d4
build/parser: Fix CPU's args_read.
2022-11-06 21:51:29 +01:00
621c5cc187
build/argument_parser: Rename to parser to simplify name/imports.
2022-11-06 21:45:07 +01:00
6b541fb4fb
build/nextpnr/yosys_wrapper: -x.
2022-11-06 21:21:23 +01:00
c62306d57e
build/argument_parser: Minor styles changes.
2022-11-06 21:19:17 +01:00
8040c83268
build/xilinx/platform: serie7 -> 7series.
2022-11-06 21:16:43 +01:00
b9b165d25d
Merge pull request #1418 from trabucayre/rework_toolchain_args
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build/lattice/platform: lattice_args, lattice_argdict: refactorize toolchains args
2022-11-06 21:15:36 +01:00
ad7ded9358
litex/litex/build: adding argument_parser (LiteXArgumentParser) to factorize toolchain aspects and common args
2022-11-06 11:22:49 +01:00
d061e9b9cf
build/xxx/platform: adding methods to return toolchains list by device, and args by toolchain
2022-11-06 11:22:32 +01:00
38ee44a85a
axi/axi_full: size/lock width are different on AXI3 and AXI4.
2022-11-04 12:35:09 +01:00
8f459a27dd
integration/common/get_mem_data: Remove dead code (thanks @Rongronggg9).
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See: https://github.com/enjoy-digital/litex/pull/1488#pullrequestreview-1168106543
2022-11-04 10:21:12 +01:00
adea7879d7
gen/fhdl/verilog: Add Verilog Timescale generation.
2022-11-04 08:15:36 +01:00
2ae445018a
Merge pull request #1489 from shenki/crc-pie-fix
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Do not build software as PIE
2022-11-04 07:52:45 +01:00
3a5a2b5c7d
Merge pull request #1488 from Icenowy/wide-soc
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Misc changes for a wider SoC
2022-11-04 07:49:27 +01:00
Florent Kermarrec
Icenowy Zheng
Mateusz Karlic
Gwenhael Goavec-Merou