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9837 Commits

Author SHA1 Message Date
Florent Kermarrec f181eabebb soc/init_rom: Add SoCError when ROM Size < Contents Size and cosmetic cleanups. 2024-04-02 09:12:03 +02:00
AndrewD 0601bf51c4
Merge pull request #1856 from motec-research/soc_initialize_memory 
soc/builder: add initialize_memory()
 2024-04-02 17:30:12 +11:00
Andrew Dennison 0cb101da25 build/efinix/platform: fix get_pin_name() 
get_pin_name did not include the resource index, so additional core
instances were generated with identical pin names. See below for
examples.

Also only adds slice index for slices with more than one io for cleaner
naming.

("i2c", 0,
    Subsignal("scl", Pins(...)),
    Subsignal("sda", Pins(...)),
),
("i2c", 1,
    Subsignal("scl", Pins(...)),
    Subsignal("sda", Pins(...)),
),

Before:
    output wire          i2c0_oe,
    input  wire          i2c0_scl,
    input  wire          i2c0_sda,
    input  wire          i2c1_scl,
    input  wire          i2c1_sda,
    input  wire          i2c_scl0_IN,
    input  wire          i2c_scl0_IN_1,
    input  wire          i2c_scl0_IN_2,
    output wire          i2c_scl0_OE,
    output wire          i2c_scl0_OE_1,
    output wire          i2c_scl0_OE_2,
    input  wire          i2c_sda0_IN,
    input  wire          i2c_sda0_IN_1,
    input  wire          i2c_sda0_IN_2,
    output wire          i2c_sda0_OE,
    output wire          i2c_sda0_OE_1,
    output wire          i2c_sda0_OE_2,

After:
    output wire          i2c0_oe,
    input  wire          i2c0_scl,
    input  wire          i2c0_scl_IN,
    output wire          i2c0_scl_OE,
    output wire          i2c0_scl_OUT,
    input  wire          i2c0_sda,
    input  wire          i2c0_sda_IN,
    output wire          i2c0_sda_OE,
    output wire          i2c0_sda_OUT,
    input  wire          i2c1_scl,
    input  wire          i2c1_scl_IN,
    output wire          i2c1_scl_OE,
    output wire          i2c1_scl_OUT,
    input  wire          i2c1_sda,
    input  wire          i2c1_sda_IN,
    output wire          i2c1_sda_OE,
    output wire          i2c1_sda_OUT,
 2024-04-02 11:52:31 +11:00
Andrew Dennison a763e82d86 soc/builder: add initialize_memory() 
Allows the target soc to override memory initialization:
  rom and/or ram.
 2024-04-02 11:37:31 +11:00
David A Roberts 5d2676482f sim/video: Add option to render only on frame vsync 2024-03-29 11:24:16 +10:00
Florent Kermarrec 87137c3027 CHANGES.md: Update. 2024-03-28 14:24:12 +01:00
enjoy-digital 7b0985a6bc
Merge pull request #1909 from davidar/sim-rgba 
sim/video: Change pixel format to RGBA
 2024-03-28 14:21:24 +01:00
enjoy-digital c73f310179
Merge pull request #1908 from Irvise/neorv32_update 
Update NeoRV32 CPU to v1.9.7
 2024-03-28 14:20:59 +01:00
Dolu1990 206118c427 Add missing file 2024-03-28 09:16:25 +01:00
Dolu1990 c7b2393e34 nax jtag renaming 2024-03-28 09:16:19 +01:00
Florent Kermarrec 60920f3c7d integration/export: Also fix MockCSRRegion base definition. 2024-03-27 17:09:33 +01:00
Florent Kermarrec e74b7f7ebe integration/export: Fix MockCSRRegion C header export. 
Use full address for export since when used, CSR_BASE is related to the top level SoC and not to the imported external mapping.
 2024-03-27 16:49:09 +01:00
David A Roberts 1895dd36e2 tools/litex_sim: Add --with-video-colorbars option 2024-03-26 20:23:51 +10:00
David A Roberts 6735728340 sim/video: Change pixel format to RGBA 2024-03-26 20:22:58 +10:00
Florent Kermarrec 4389742a4f CHANGES.md: Update. 2024-03-25 19:10:40 +01:00
Fernando Oleo Blanco 40ff2da45c Update NeoRV32 CPU to v1.9.7 2024-03-23 10:18:07 +01:00
Gwenhael Goavec-Merou 9156d7902e tools/litex_json2dts_linux: increment interrupts value by one for rocket 2024-03-21 20:54:08 +01:00
Gwenhael Goavec-Merou 68108e396d tools/litex_json2dts_linux: added isa-base,isa-extensions required by kernel > 6.6.0 in replacement to isa 2024-03-21 20:53:19 +01:00
Dolu1990 473c52c9d8 Got jtag instruction interface to work 2024-03-21 13:29:40 +01:00
Dolu1990 72cb7d3fb7 Fix jtag reset 2024-03-21 13:05:18 +01:00
enjoy-digital 29aa8f0771
Merge pull request #1906 from jdavidberger/master 
Avoid extra timing delays for NXLRAM path
 2024-03-21 09:14:39 +01:00
jdavidberger c640efcec3 Avoid extra timing delays for NXLRAM path 2024-03-20 14:58:08 -06:00
Dolu1990 90c1d7b62d Update the reset topology 2024-03-20 17:56:53 +01:00
Dolu1990 edc24b39a4 Got linux + jtag to run in sim 2024-03-20 17:37:51 +01:00
Gwenhael Goavec-Merou 8f04542c15 Revert "build/openocd: Allow config file to be searched from local dirs" 
This reverts commit a7d441488c.
 2024-03-20 16:44:58 +01:00
Gwenhael Goavec-Merou 46ff7cdee5
Merge pull request #1901 from FlyGoat/zynq7000_openocd 
Zynq7000 litex_server OpenOCD JTAG fixes
 2024-03-20 16:41:22 +01:00
Dolu1990 d7a862fdd0 wip 2024-03-20 08:09:30 +01:00
inc 9d0fc2c7c2 litex_json2dts_linux: Add support for multiple Ethernet interfaces 2024-03-12 14:42:48 +01:00
Florent Kermarrec c2fd1e9a49 litex_json2dts_linux: Switch to cpu_name instead of cpu_human_name. 2024-03-08 18:53:44 +01:00
Florent Kermarrec 49f12ea297 soc/add_cpu: Add CPU_NAME constant. 2024-03-08 18:51:26 +01:00
Jiaxun Yang a7d441488c build/openocd: Allow config file to be searched from local dirs 
To sort out path for boards using OpenOCD config file shipped with
OpenOCD itself.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2024-03-07 19:54:04 +00:00
enjoy-digital 94e644ba92
Merge pull request #1902 from trabucayre/rocket_update 
Rocket update
 2024-03-07 13:38:02 +01:00
Gwenhael Goavec-Merou 68991b6a40 tools/litex_json2dts_linux: added missing rocket's nodes (align to pythondata-cpu-rocket dts) 2024-03-07 11:59:48 +01:00
Gwenhael Goavec-Merou 54f8d90d38 soc/cores/cpu/rocket/core: align config (XCACHE, XTLB) to pythondata-cpu-rocket master 2024-03-07 09:00:32 +01:00
Florent Kermarrec 149080fc8b cpu/naxriscv/core: Minor cleanups and add xlen to human_name. 2024-03-06 16:01:38 +01:00
Jiaxun Yang 18720e29cc build/openocd: Fix tap name for zynq_7000 
zynq_7000 have a special tap name fpr PL defined in openocd
config file.

Just hardcode it here.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2024-03-05 21:44:55 +00:00
Jiaxun Yang 35dd87499c build/openocd: Disable polling after init 
OpenOCD's event polling mechanism may interfere with
jtagstream, as we don't expect any command sent by
openocd itself.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2024-03-05 21:34:56 +00:00
enjoy-digital f304cba8a6
Merge pull request #1897 from machdyne/master 
support TQFP144 ECP5 package
 2024-03-05 21:26:22 +01:00
enjoy-digital 98c15331be
Merge pull request #1899 from meiniKi/fazyrv_path 
FazyRV: Fix minor typo in path check
 2024-03-05 21:24:49 +01:00
Gwenhael Goavec-Merou 1511c8f200 tools/litex_json2dts_linux: don't hardcode phandle for clint's interrupts-extended 2024-03-05 16:10:42 +01:00
Meinhard Kissich 12b9c8b2e7 cpu/fazyrv: Fix minor path typo 2024-03-04 21:44:18 +01:00
Gwenhael Goavec-Merou 044760e06c build/colognechip/colognechip: check if p_r is in PATH before trying to copy dly file 2024-03-02 12:23:10 +01:00
Florent Kermarrec 62f275debd cpu/fazyrv: Expose parameters and fix vdir. 
On your targets: --cpu-type=fazyrv --help:

CPU options.:
  --cpu-chunksize {1,2,4,8}
          Size of the chunks, i.e., the data path. (default: 8)
  --cpu-conf {MIN,INT,CSR}
          Configuration of the processor. (default: MIN)
  --cpu-rftype {LOGIC,BRAM,BRAM_BP,BRAM_DP,BRAM_DP_BP}
          Implementation of the register file. (default: BRAM_DP_BP)

Then: litex_sim --cpu-type=fazyrv --cpu-chunksize=4 --cpu-rftype=LOGIC

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar  1 2024 10:49:12
 BIOS CRC passed (a3cd3faa)

 LiteX git sha1: 45835b4b

--=============== SoC ==================--
CPU:		FazyRV-STANDARD @ 1MHz
BUS:		wishbone 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2024-03-01 10:49:37 +01:00
Gwenhael Goavec-Merou 45835b4b9d build/colognechip/colognechip: workaround for p_r complaining about a missing dly file (will be fixed by the next CologneChip's toolchain release) 2024-03-01 07:12:11 +01:00
Florent Kermarrec 697fb51a32 soc/cores/cpu: Add initial FazyRV support with default variant. 
It will then be useful to expose the different parameters or create variants.

litex_sim --cpu-type=fazyrv:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar  1 2024 06:49:55
 BIOS CRC passed (1ee1fd74)

 LiteX git sha1: 4ca66bbe

--=============== SoC ==================--
CPU:		FazyRV-STANDARD @ 1MHz
BUS:		wishbone 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2024-03-01 06:52:02 +01:00
inc eeeffa9ffd support TQFP144 ECP5 package 2024-02-29 21:30:25 +01:00
Florent Kermarrec 4ca66bbee6 interconnect/wishbone/Remapper: Fix src_adr/dst_adr signal size. 2024-02-28 19:11:59 +01:00
Florent Kermarrec 722b6da9fb test/test_wishbone: Improve origin_region_remap_test to test more complex remapping. 2024-02-28 19:11:55 +01:00
Gwenhael Goavec-Merou 3d9db91387 build/colognechip/colognechip: add missing p_r option (-cCP) 2024-02-28 17:17:42 +01:00
Gwenhael Goavec-Merou 83c1adbc94 soc/cores/clock/colognechip: set lock_req to 1 by default and connect locked to USR_PLL_LOCKED_STDY 2024-02-28 17:17:06 +01:00