Commit Graph

4285 Commits

Author SHA1 Message Date
Florent Kermarrec fcd518b5d0 bios/boot: add specific flash_boot for linux with vexriscv 2019-05-04 11:27:01 +02:00
Florent Kermarrec 1ba1ad9a00 bios/boot: rename MM_RAM to EMULATOR_RAM 2019-05-03 19:47:36 +02:00
Florent Kermarrec fbb24720f0 soc/get_mem_data: add direct support for regions
We now support passing filename (offset=0), json file and regions
2019-05-03 13:24:06 +02:00
Florent Kermarrec 0714816f31 soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone 2019-05-03 11:59:06 +02:00
Florent Kermarrec c6d0d23445 soc/interconnect/axi: add AXI Lite definition 2019-05-03 09:43:12 +02:00
Florent Kermarrec 9fab4752c4 soc/interconnect/axi: add comment on axi signas that are present but not used 2019-05-03 09:30:59 +02:00
Florent Kermarrec 5989076346 cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant 2019-05-03 09:30:26 +02:00
Florent Kermarrec 21bf10383d bios/boot: add liftoff banner just before booting 2019-05-02 18:26:35 +02:00
Florent Kermarrec 8f4685b3b1 bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config 2019-05-02 16:34:41 +02:00
Florent Kermarrec 6cf1ff091c soc/interconnect/axi: connect axi.ar/aw when selecting write or read 2019-05-02 09:58:55 +02:00
Florent Kermarrec 6affc56a09 soc/interconnect/axi: wishbone address shift is not always 2, make it generic 2019-05-02 09:35:07 +02:00
Florent Kermarrec 698bc88296 soc/interconnect/wishbone: allow setting adr_width (default to 30) 2019-05-02 09:34:30 +02:00
Florent Kermarrec 4dccb8a9eb soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent 2019-05-01 12:59:04 +02:00
Florent Kermarrec 9f8f0eb18e build/sim: update tapcfg 2019-05-01 12:34:12 +02:00
enjoy-digital 2515c7b0b5
Merge pull request #176 from gsomlo/gls-ulong-addr
software: use "unsigned long" for address values, also 8-byte alignment
2019-05-01 12:09:18 +02:00
Gabriel L. Somlo 5c2b8685fc software: use "unsigned long" for address values, also 8-byte alignment
Enable future support for 64-bit CPU models.
2019-04-29 15:03:38 -04:00
Florent Kermarrec 74d37465b3 test/test_targets: comment bad variant tests for now 2019-04-29 17:11:42 +02:00
Florent Kermarrec 5c1d980540 soc/interconnect/axi: add burst support to AXI2Wishbone 2019-04-29 16:49:20 +02:00
Florent Kermarrec 6de2713524 soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize 2019-04-29 14:02:05 +02:00
Florent Kermarrec 305b8879de integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k)
Keep or1k retro-compatibility for now but add a warning
2019-04-29 10:14:30 +02:00
Florent Kermarrec 4e50f36b72 build/tools: add deprecated_warning 2019-04-29 10:12:54 +02:00
Florent Kermarrec b40d1b73c4 cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) 2019-04-29 10:00:04 +02:00
Florent Kermarrec dbb71af189 cpu: use property methods to return name, endianness, gcc triple/flags, linker output format 2019-04-29 09:58:51 +02:00
Florent Kermarrec d828c3a596 cpu: integrate nmigen version of Minerva, add submodule 2019-04-28 23:40:33 +02:00
Florent Kermarrec 2c3c6bdf9b Updating documents from LiteX BuildEnv Wiki 2019-04-28 11:41:33 +02:00
Kurt Kiefer bf27869ad9 fix vexriscv build 2019-04-28 11:10:20 +02:00
enjoy-digital 2d5bae3def
Merge pull request #175 from mithro/cpu-docs
Standardizing `cpu_variants` and adding lots of documentation
2019-04-27 21:24:06 +02:00
Tim 'mithro' Ansell 5cbc5bc199 Adding testing of cpu variants. 2019-04-26 18:57:49 -05:00
Tim 'mithro' Ansell 71a837315a Work with no `cpu_variant` provided. 2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell 65650919a7 Updating documents from LiteX BuildEnv Wiki 2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell a43de8195f Updating documents from LiteX BuildEnv Wiki 2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell 39c579baa2 Standardize the `cpu_variant` strings.
Current valid `cpu_variant` values;
 * minimal  (alias: min)
 * lite     (alias: light, zephyr, nuttx)
 * standard (alias: std) - Default
 * full     (alias: everything)
 * linux

Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki).

Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
2019-04-26 17:44:30 -05:00
Florent Kermarrec 3a2e283613 .gitmodules: use our VexRiscv-verilog 2019-04-27 00:00:55 +02:00
Tim 'mithro' Ansell e42de8fe52 docs: Adding script to pull useful docs from LiteX BuildEnv's wiki. 2019-04-26 14:28:20 -05:00
Florent Kermarrec 78c09125be soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes 2019-04-25 23:43:10 +02:00
Florent Kermarrec 0175f86cb2 soc/integration/soc_core: fix get_mem_data for json files 2019-04-25 18:36:47 +02:00
Florent Kermarrec 4443b5075b soc/integration/soc_core: add integrated_sram_init 2019-04-25 17:30:03 +02:00
Florent Kermarrec f27084c6c0 soc/integration/cpu_interface: fix banner in get_mem_header 2019-04-24 22:44:37 +02:00
enjoy-digital 5ec99d94ae
Merge pull request #173 from gsomlo/gls-git-revision
build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 22:42:36 +02:00
Gabriel L. Somlo d21cba2f17 build: handle exceptional case when litex/migen not deployed as git repo 2019-04-24 12:50:47 -04:00
Florent Kermarrec 27fbb814ab tools/remote/csr_builder: allow comments in csv file and cleanup 2019-04-24 12:25:49 +02:00
Florent Kermarrec e8f3c49127 software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding 2019-04-24 11:32:40 +02:00
Florent Kermarrec 44e0cdda9a software/libnet/microudp: speed-up ARP by changing timeout/tries
First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
2019-04-24 09:55:41 +02:00
Florent Kermarrec 3ee78a5b70 build/tools: fix typo 2019-04-23 18:10:51 +02:00
Florent Kermarrec f0fe9f3cdf setup.py: add short names for tools 2019-04-23 17:46:20 +02:00
Florent Kermarrec 9ded2eb20b tools/litex_term: change TERM prompt to LXTERM 2019-04-23 17:46:02 +02:00
Florent Kermarrec 475deb51ac build: add migen and litex git revision to generated file 2019-04-23 17:40:24 +02:00
Florent Kermarrec 8b5cf29542 build/tools: git_revision is not doing what we want, return "--------" for now 2019-04-23 17:15:43 +02:00
Florent Kermarrec 228f286747 litex_setup: revert default install behaviour but add --user support 2019-04-23 14:53:00 +02:00
enjoy-digital 9fbbf928ed
Merge pull request #171 from keesj/develop_as_user
Install development packages in the user directory
2019-04-23 14:41:37 +02:00