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Dolu1990-patch-1

Dolu1990-patch-2

Dolu1990-patch-3

allows_clk_name_override

ci-cpus

ci-cva6

ci-dev-test

ci-openrisc

ctu-can-fd

dma_nax

efinix_fixes

efinix_fixes2

efinix_iface_signal_names

export_csr_c_rework

framebuffer_change

generic_toolchain

ghdl_fix

gowin_emcu_uart

hyperbus_2x

hyperbus_io_regs

hyperbus_variable_latency

hyperram_decoupling

hyperram_new

kianv

liteeth_wishbone_tx_rx_buses

master

multi-channel-pwm

naxriscv-merge

naxriscv_update

neorv32_litex_wrapper

neorv32_params

urv

usb_ohci_phy_fix

verilog_improvements

verilog_improvements_2

vexriscv_smp_irqs

video_framebuffer_skip_first_frame

video_mod_fix

wishbone_dma_ctrl

wishbone_word_byte_addressing

wuff

zynqmp_aximaster_eth_i2c_uart

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f8dc03810d build: efinix: use LiteXContext to get platform Fin Maaß 2024-09-26 15:48:31 +0200
afcc477c4e efinix: common: replace is_inclk_inverted Fin Maaß 2024-09-25 11:10:18 +0200
a605e75873 efinix: ifacewriter: remove deprecated GPIO properties Fin Maaß 2024-09-25 11:04:59 +0200
2c3536720c efinix: ifacewriter: add in_clk_inv for GPIO INPUT block Fin Maaß 2024-09-25 11:00:50 +0200
10ab1b76c0 efinix: ifacewriter: fix out_reg in GPIO INOUT block Fin Maaß 2024-09-25 10:59:39 +0200
a5747232d5

Merge b4c4e890e5 into b135f71512 Fin Maaß 2024-09-26 13:20:04 +0200
b135f71512 build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated. Florent Kermarrec 2024-09-26 12:58:54 +0200
b5e91473b7 build/efinix/common: Update EfinixSDRInputImpl and minor cleanup. Florent Kermarrec 2024-09-26 11:50:37 +0200
0e337e2079

Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input enjoy-digital 2024-09-26 11:43:20 +0200
a19fbb70c4

Merge pull request #2078 from VOGL-electronic/efinix_add_ipm enjoy-digital 2024-09-26 11:42:34 +0200
b11cc8c3eb

Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names enjoy-digital 2024-09-26 11:42:02 +0200
39d292a3c7 build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names. efinix_iface_signal_names Florent Kermarrec 2024-09-26 10:37:54 +0200
a3a55fc8fb build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names. Florent Kermarrec 2024-09-26 10:14:42 +0200
fde9d2e4ad build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks. Florent Kermarrec 2024-09-26 10:12:33 +0200
61f715e6e7

build: efinix: common.py; add SDRInput Fin Maaß 2024-09-25 17:17:53 +0200
c3e87367c3 soc/cores/vexriscv_smp: Add the generation of the default sim config (https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405) Dolu1990 2024-09-25 10:38:20 +0200
b86d76baed build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations. Florent Kermarrec 2024-09-25 08:53:57 +0200
8a6264c4f6

build: efinix: add function to add ip Fin Maaß 2024-09-24 11:59:28 +0200
c95a6e041c soc/interconnect/stream: Add Delay module. Florent Kermarrec 2024-09-23 12:23:29 +0200
b2f63b37cc CHANGES.md: Update. Florent Kermarrec 2024-09-20 13:00:40 +0200
427ec10cc4 CONTRIBUTORS: Update. Florent Kermarrec 2024-09-20 12:43:18 +0200
726d39f40d LICENSE: Bump year. Florent Kermarrec 2024-09-20 12:39:28 +0200
b4c4e890e5

build: efinix: implement QDR input, output and tristade. Fin Maaß 2024-09-19 11:13:22 +0200
68d5e590dd build: io.py: add QDR input, output and tristate Fin Maaß 2024-09-19 11:11:20 +0200
baff4c69fe

Merge pull request #2075 from trabucayre/efinix_clkinput_signal enjoy-digital 2024-09-19 11:59:06 +0200
033ec13f08

Merge pull request #2076 from trabucayre/xc7s_jtag enjoy-digital 2024-09-19 11:53:55 +0200
6e9dffdbf5 soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when building with Vivado). Florent Kermarrec 2024-09-19 11:10:51 +0200
ad2c3fcea7 soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without specifying --cpu-variant. Florent Kermarrec 2024-09-19 09:21:13 +0200
f1e1f3530e build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio) Gwenhael Goavec-Merou 2024-09-19 09:14:30 +0200
aca959b059 build/efinix/common.py: ClkInput: added ClockSignal support Gwenhael Goavec-Merou 2024-09-18 15:25:20 +0200
e072156b93 build/xilinx/platform.py: added xc7s to the list of device supporting jtag access Gwenhael Goavec-Merou 2024-09-19 06:49:44 +0200
fc68f031a1 soc/cores/jtag.py: added Spartan7 definition for BSCANE2 Gwenhael Goavec-Merou 2024-09-19 06:49:10 +0200
9bacbe130b

Merge pull request #1974 from motec-research/dts_zephyr_updates enjoy-digital 2024-09-17 14:58:51 +0200
1c583e4eaf

litex_setup: use current version of migen Fin Maaß 2024-09-16 11:41:33 +0200
a350d2e909 soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux. Florent Kermarrec 2024-09-13 19:21:16 +0200
2a19a61e05 build/xilinx/vivado: Fix typo. Florent Kermarrec 2024-09-13 10:39:13 +0200
99550809b3

Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet enjoy-digital 2024-09-13 08:36:40 +0200
dc8c1bd9cd build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for consistency with other directives. Florent Kermarrec 2024-09-12 18:04:25 +0200
203c9816b2 integration/soc/add_etherbone: Allow 64-bit support now that validated. Florent Kermarrec 2024-09-12 13:38:13 +0200
4549bf11ea

Merge branch 'enjoy-digital:master' into master Joris Lee 2024-09-12 17:04:39 +0800
2fd8c2cd61 sim: add HW_PREAMBLE_CRC for ethernet Matthias Breithaupt 2024-09-12 08:22:00 +0200
b41a526e81

Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac enjoy-digital 2024-09-11 11:54:14 +0200
11c7b69fd4

Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix enjoy-digital 2024-09-11 11:53:52 +0200
7b3f1509d1

soc.py: add_ethernet: add mac addr constant Fin Maaß 2024-09-11 11:21:53 +0200
3966e3438c

bios: boot.c: fix warnings Fin Maaß 2024-09-11 11:15:56 +0200
dc8b74cc58

Merge pull request #2060 from Dolu1990/efinix-rework Gwenhael Goavec-Merou 2024-09-10 18:40:10 +0200
a80f290d80 soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name Gwenhael Goavec-Merou 2024-09-10 18:07:34 +0200
ad09ffc150 soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str Gwenhael Goavec-Merou 2024-09-10 18:01:40 +0200
109ae17e9e build/efinix/common.py: replaced i as str by a ClockDomain Gwenhael Goavec-Merou 2024-09-10 17:56:49 +0200
d1aec39a62 soc/cores/clock/efinix.py: create_clkin try to extract input_signal from name OR from clkin Gwenhael Goavec-Merou 2024-09-10 16:34:09 +0200
0d5fb367da build/efinix/ifacewriter.py: LVDS: when clk is a clockSignal uses platform.clk mapping dict to obtain signal name Gwenhael Goavec-Merou 2024-09-10 15:44:05 +0200
3e20fcd16c build/efinix/platform.py: added a list to store mapping between cd name and signals name (WIP) Gwenhael Goavec-Merou 2024-09-10 15:42:35 +0200
438c12b6df soc/cores/clock/efinix.py: push mapping between cd names and signal name (WIP) Gwenhael Goavec-Merou 2024-09-10 15:41:29 +0200
bdebbad1b4

Merge cd3364a433 into 458e0057f2 AndrewD 2024-09-10 14:12:20 +0200
8e1bb6b333 build/efinix/common.py: ClkOutput now must receive a ClockSignal Gwenhael Goavec-Merou 2024-09-10 11:26:48 +0200
b3a7ceb16d soc/cores/clock/efinix.py: uses self.name for clk_name, remove add_period_constraints Gwenhael Goavec-Merou 2024-09-10 11:08:17 +0200
276aa6e00a soc/cores/clock/efinix.py: added pll+id in clkout name Gwenhael Goavec-Merou 2024-09-10 08:16:17 +0200
e5f2d43ae3 litex/build/efinix/common.py add EfinixDDRTristate binding Dolu1990 2024-09-05 16:12:32 +0200
9d751e9ab1 build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled Dolu1990 2024-09-05 15:21:12 +0200
458e0057f2 soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths. Florent Kermarrec 2024-09-09 18:18:59 +0200
5cd1a57080 soc/interconnect/wishbone: Cosmetic cleanup on Cache. Florent Kermarrec 2024-09-09 18:16:40 +0200
e06045c576

Merge pull request #2059 from Dolu1990/vexii-clk-video enjoy-digital 2024-09-09 14:12:50 +0200
2db93c8e78 core/vexiiriscv: improve l2 timings Dolu1990 2024-09-06 16:05:34 +0200
a1a3e846ac

Merge pull request #2058 from VOGL-electronic/bios_add_spiram enjoy-digital 2024-09-06 08:32:11 +0200
bd03c496a1 bios: add spiram Fin Maaß 2024-09-05 12:02:28 +0200
599c6dde37

litex/build/efinix/common.py add EfinixDDRTristate binding Dolu1990 2024-09-05 16:12:32 +0200
c0fddb6561 build/efinix: add a few IO primitives, IO constraints, but mainly it rework how the SDC are handled Dolu1990 2024-09-05 15:21:12 +0200
642cfbe9a7 soc/cores/vexiiriscv: update clocks + add video framebuffer support Dolu1990 2024-09-05 15:16:15 +0200
e62d84b77b Revert "soc/cores/vexiiriscv: update clocks + add video framebuffer support" Dolu1990 2024-09-05 15:15:49 +0200
0ea6dd91aa soc/cores/vexiiriscv: update clocks + add video framebuffer support Dolu1990 2024-09-05 15:13:35 +0200
fa47c62b6d

Merge pull request #2057 from Dolu1990/usb_ohci_phy_fix2 enjoy-digital 2024-09-05 14:40:34 +0200
f512c65077 vexiiriscv git update Dolu1990 2024-09-05 13:17:22 +0200
2190ca403a core/usb_ohci: fix SDRTristate clock Dolu1990 2024-09-05 10:17:22 +0200
f67b39739e soc/integration/add_ethernet: Expose full_memory_we parameter. Florent Kermarrec 2024-09-05 10:18:12 +0200
1f2418de3b core/usb_ohci: fix SDRTristate clock usb_ohci_phy_fix Dolu1990 2024-09-05 10:17:22 +0200
84e7e816c7 efinix: pll now force the generated clock into cd.clk *WARNING* Dolu1990 2024-09-05 10:16:43 +0200
d3161ad74c build/efinix/platform: fix get_pin_name() Andrew Dennison 2024-02-26 03:32:50 +0000
eda553aeaa

Merge pull request #2056 from trabucayre/altera_agilex5_asyncresetsynchronizer enjoy-digital 2024-09-03 17:54:27 +0200
d0215001f4 build/altera/common: added special AsyncResetSynchronizer based on altera_std_synchronizer_nocut Gwenhael Goavec-Merou 2024-09-03 17:47:40 +0200
a90ab9dcca efinix: Merge pt.sdc to the litex sdc to get constraints right Dolu1990 2024-09-03 12:05:26 +0200
dc29b6f4e5 CHANGES.md: Update. Florent Kermarrec 2024-09-03 09:43:29 +0200
4152d22065 Revert "build/efinix/platform: fix get_pin_name()" Gwenhael Goavec-Merou 2024-09-03 08:51:39 +0200
3de5832b9c vexiiriscv: Now use pll.locked for debug reset Dolu1990 2024-09-03 07:58:24 +0200
19b3f24d9f efinix: ifacewriter support drive strength and slew Dolu1990 2024-09-03 07:57:30 +0200
e01ce6f948 efinix: ifacewriter support drive strength and slew Dolu1990 2024-09-03 07:55:25 +0200
3bdbe1ebcf CHANGES.md: Update. Florent Kermarrec 2024-09-02 14:20:09 +0200
af0dc7f98b

Merge pull request #2055 from trabucayre/gowin_apicula_fix enjoy-digital 2024-09-02 14:08:07 +0200
babe233407 build/gowin/apicula: only append _packer_opts with known use_xxx (drop options only required by Gowin's software) Gwenhael Goavec-Merou 2024-09-01 09:55:01 +0200
3da470048a build/gowin/apicula: append _synth_opts with specific requirements according to FPGA model Gwenhael Goavec-Merou 2024-09-01 09:53:24 +0200
658774c965

Merge 222848298f into 15cd556750 AndrewD 2024-08-31 17:26:52 -0400
2f2b292e06 vexii add with-cpu-clk Dolu1990 2024-08-30 18:16:56 +0200
15cd556750

Merge pull request #2053 from enjoy-digital/hyperram_new enjoy-digital 2024-08-30 15:38:59 +0200
61b54aa491 soc/integration/soc: Fix add_peripheral. Florent Kermarrec 2024-08-30 12:08:00 +0200
c554752e8a soc/cores/hyperbus: Add automatic read burst detection. hyperram_new Florent Kermarrec 2024-08-29 19:39:56 +0200
c14f1d0816 vexiiriscv add video support Dolu1990 2024-08-30 10:44:36 +0200
5fb873d209 efinix: Add support for more IO Dolu1990 2024-08-30 10:44:10 +0200
3bde3e9848 soc/cores/hyperbus: Add automatic write burst detection. Florent Kermarrec 2024-08-29 16:24:12 +0200
fac80c3a51 soc/cores/hyperbus: Full rewrite of HyperRAM core. Florent Kermarrec 2024-08-26 11:24:16 +0200
cc3f13670a Merge pull request #2050 from Dolu1990/efinix_pll_ext_fix Dolu1990 2024-08-28 20:13:03 +0200
d4003b8cfa efinix add SCHMITT_TRIGGER support Dolu1990 2024-08-28 19:59:30 +0200