Hardware
/
picorv32
mirror of https://github.com/YosysHQ/picorv32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
331 Commits 2 Branches 1 Tag 2.8 MiB
Commit Graph

331 Commits

Author SHA1 Message Date
Clifford Wolf 1a664f9b97 Changed chip package in vivado examples 2015-06-26 10:46:51 +02:00
Clifford Wolf 5d4ce82050 Implemented waitirq instruction 2015-06-26 10:39:08 +02:00
Clifford Wolf 9a4a06d981 Refactoring of IRQ handling 2015-06-26 10:03:37 +02:00
Clifford Wolf 9d26ebcf58 Improvements in README.md 2015-06-25 14:14:07 +02:00
Clifford Wolf 23b700cf73 Added basic IRQ support 2015-06-25 14:08:39 +02:00
Clifford Wolf 982e5cc600 Added simple icestorm script (not a real example yet) 2015-06-22 11:35:48 +02:00
Clifford Wolf 8590c7d2a8 Updated Vivado SoC example 2015-06-10 16:48:06 +02:00
Clifford Wolf 26127b45de Makefile for Vivado scripts 2015-06-09 12:45:45 +02:00
Clifford Wolf b4b1d03b1c More Todos 2015-06-09 10:01:00 +02:00
Clifford Wolf bb7f500489 Removed unnecessary "jal" complexity 2015-06-09 07:40:30 +02:00
Clifford Wolf 0257d2cb08 Small improvements in vivado_soc demo 2015-06-08 19:58:28 +02:00
Clifford Wolf 072e5ca2c5 Added osu018 yosys synthesis script 2015-06-08 09:31:56 +02:00
Clifford Wolf a9532f81ed Refactored instruction decoder 2015-06-08 09:08:19 +02:00
Clifford Wolf 32208c0b70 Improved timing for "decoded_imm_uj" 2015-06-07 22:50:49 +02:00
Clifford Wolf 06ba3a1a57 README Updates 2015-06-07 20:59:20 +02:00
Clifford Wolf 34d9dea8c7 Added support for dual-port register file 2015-06-07 20:53:19 +02:00
Clifford Wolf 60867e10a9 minor optimizations 2015-06-07 20:08:04 +02:00
Clifford Wolf 8e3e0bfba0 Improved "decoder_trigger" handling 2015-06-07 19:49:38 +02:00
Clifford Wolf bbbcea2faa Added look-ahead write interface 2015-06-07 12:11:20 +02:00
Clifford Wolf e84f044bc5 Major redesign of main FSM 2015-06-07 11:49:47 +02:00
Clifford Wolf 491cd5e15d Using libc assembler code in dhrystone stdlib.c 2015-06-07 07:29:13 +02:00
Clifford Wolf 44ea992fed Updated CPI table in README 2015-06-06 21:43:33 +02:00
Clifford Wolf 90ff3380a4 Updated README 2015-06-06 21:27:58 +02:00
Clifford Wolf 2107a328c4 Added insn timing hack to dryhstone testbench 2015-06-06 21:27:07 +02:00
Clifford Wolf bc8ffd2ecb Added memory "look-ahead" read interface 2015-06-06 20:50:53 +02:00
Clifford Wolf 9df9d7ff90 Improved Xilinx example 2015-06-06 20:14:58 +02:00
Clifford Wolf abe0465753 Faster memory model in dhrystone testbench 2015-06-06 19:35:07 +02:00
Clifford Wolf c55d537401 Improved AXI tests 2015-06-06 19:22:28 +02:00
Clifford Wolf f9ae73066b Added license info to README 2015-06-06 17:24:11 +02:00
Clifford Wolf 7fd24a96b2 Improved AXI Interface Testbench 2015-06-06 17:15:09 +02:00
Clifford Wolf 77ba5a1897 Initial import 2015-06-06 14:14:32 +02:00