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picorv32

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• 822e2d4a77 Added more comments to file NickAA 2023-01-29 16:31:15 -0500
• f3e8415171 Added Menu to control_loop_sim.cpp NickAA 2023-01-29 16:25:24 -0500
• 195a9c5042 boilerplate.cpp: remove Peter McGoron 2023-01-28 00:25:09 +0000
• c7dadc5681 bram: more refactor Peter McGoron 2023-01-27 22:58:29 +0000
• 285b6d9501 refactor bram interface simulation Peter McGoron 2023-01-27 22:27:20 +0000
• c68027f24f Merge branch 'master' of ssh://github.com/phm19a/upsilon Peter McGoron 2023-01-23 05:00:08 +0000
• b1ba3434cf autoapproach: add reset test to bram Peter McGoron 2023-01-23 04:58:38 +0000
• 65b1436e0b autoapproach: test refreshing bram Peter McGoron 2023-01-23 04:47:12 +0000
• 034f76da41 autoapproach: add bram and test Peter McGoron 2023-01-23 04:43:51 +0000
• 00ac3e03dc Added comments NickAA 2023-01-20 15:24:24 -0500
• 7ceaa730d9 remove hardcoded P and I changes Peter McGoron 2023-01-12 19:19:19 +0000
• ca5105a6bb start rewrite kernel Peter McGoron 2023-01-01 21:10:02 +0000
• f8bf634345 reorganization; remove json Peter McGoron 2022-12-31 20:15:24 +0000
• 6604e35b89 autoapproach draft #1 Peter McGoron 2022-12-28 19:32:35 +0000
• 96e9a3d043 raster simulate Peter McGoron 2022-12-23 20:22:48 +0000
• 013774e28b raster_sim: rewrite to fit new module definitions Peter McGoron 2022-12-21 05:56:49 +0000
• a79ace9568 raster_cmds: add Peter McGoron 2022-12-21 05:24:33 +0000
• a918d74f05 introduce control interface; pack adc_data bits into large vector instead of an array Peter McGoron 2022-12-21 05:16:15 +0000
• ac0ed9e2a7 yosys does not support input arrays Peter McGoron 2022-12-20 06:25:45 +0000
• a2acccbca6 misc Peter McGoron 2022-12-20 06:07:54 +0000
• c52f649313 programmers manual Peter McGoron 2022-12-20 05:51:30 +0000
• 4ba004336c ram_shim: simulate Peter McGoron 2022-12-20 05:51:05 +0000
• 15480f11da ram_fifo: add empty and full ports Peter McGoron 2022-12-18 06:06:44 +0000
• 1be89f314c simulate and verify ram_fifo and ram_fifo_dual_port Peter McGoron 2022-12-17 18:39:58 +0000
• 60404cd026 ram_fifo.v: add simulator debugging checks Peter McGoron 2022-12-17 10:18:15 -0500
• f0f1750a9a add ram_fifo_dual_port wrapper to single port FIFO Peter McGoron 2022-12-17 10:03:06 -0500
• 3612148ee1 raster/ram_fifo: correct misspelling Peter McGoron 2022-12-17 09:56:57 -0500
• f536a41784 control_loop: remove reg keyword, yosys doesnt like it Peter McGoron 2022-12-17 09:56:26 -0500
• 644f4142a2 raster work Peter McGoron 2022-12-17 00:46:04 +0000
• ffdf4fb2f2 import Xilinx FIFO36E1 simulation Peter McGoron 2022-12-16 20:46:00 +0000
• 59b6efce7e raster_sim.v: add and lint Peter McGoron 2022-11-26 12:00:10 -0500
• a12fbf8af2 ram_shim: add and lint Peter McGoron 2022-11-26 11:53:57 -0500
• c8d7572db5 raster.v: lint Peter McGoron 2022-11-26 11:47:06 -0500
• 9282c33cce add ram shim Peter McGoron 2022-11-24 11:07:30 -0500
• 1ed48fbc90 control_loop_sim: add comments Peter McGoron 2022-11-24 10:08:00 -0500
• cef639784b control_loop_sim: modify second P value Peter McGoron 2022-11-24 10:00:05 -0500
• 1d54b41735 fix bit width bug Peter McGoron 2022-11-24 09:55:15 -0500
• 33ec8351d8 correctly (and crudely) simulate control loop Peter McGoron 2022-11-24 09:48:04 -0500
• 6ad2de97cf sketch out raster scan Peter McGoron 2022-11-24 00:50:21 -0500
• adb81e201e fix dac simulation Peter McGoron 2022-11-21 22:56:40 -0500
• 5ff6b279b0 reverify math Peter McGoron 2022-11-21 22:24:37 -0500
• 79cae3dd66 (somewhat) fix counter Peter McGoron 2022-11-21 22:08:25 -0500
• cfb0f92528 fix adc_sim Peter McGoron 2022-11-21 22:04:46 -0500
• 5909f548d5 control loop simulator passes lint Peter McGoron 2022-11-21 21:41:50 -0500
• 0114c449c3 correct simulation of control loop Peter McGoron 2022-11-19 12:55:55 -0500
• a0450fb0ff control_loop_math: fix compile errors and verify simulation Peter McGoron 2022-11-18 19:27:29 -0500
• 0c10dc921c more work on control_loop Peter McGoron 2022-11-18 19:11:56 -0500
• 3a23ac6e92 control_loop; add dirty bit to decrease the amount of comparisons Peter McGoron 2022-11-17 19:14:24 -0500
• 8d11442cbb update .gitignore Peter McGoron 2022-11-17 19:07:49 -0500
• 29e0e8dfb3 integrate control_loop_math into control_loop Peter McGoron 2022-11-17 19:07:21 -0500
• d9f4a40c6d update GUIDELINES.md Peter McGoron 2022-11-17 18:39:48 -0500
• 82ff659a44 add DAC ramp Peter McGoron 2022-11-17 17:32:32 -0500
• 0907a76c22 import spi v0.2 Peter McGoron 2022-11-14 08:43:16 -0500
• 50ea679e02 Rewrite control_loop_math and simulate Peter McGoron 2022-11-13 18:03:55 -0500
• 88c42a9f4a add printing of fixed point values in C++ Peter McGoron 2022-11-12 01:44:30 -0500
• c21e2bbb63 add calculate dt module with simulation Peter McGoron 2022-11-11 22:42:06 -0500
• 7637a1db9a import updated boothmul Peter McGoron 2022-11-11 22:14:50 -0500
• 45f815c5d3 changes Peter McGoron 2022-11-11 21:57:58 -0500
• 7a341a9632 yosys does not like calculated parameters Peter McGoron 2022-10-30 15:37:45 -0400
• 732be44a8d add guidelines Peter McGoron 2022-10-30 15:37:01 -0400
• ba901a80d7 separate math into other file Peter McGoron 2022-10-28 17:31:23 -0400
• 653040fb67 clarify licenses Peter McGoron 2022-10-27 17:55:57 -0400
• 440f144180 fixed fixed point algorithms in python Peter McGoron 2022-10-27 17:55:12 -0400
• 4f85146d61 add cycle count for each iteration Peter McGoron 2022-10-23 14:21:31 -0400
• 0a435f6dc8 rename control loop verilog simulation top level module to more descriptive name Peter McGoron 2022-10-22 01:58:37 -0400
• 7971f8ea98 change heading Peter McGoron 2022-10-22 01:55:56 -0400
• 644929ef8a move documentation to other file Peter McGoron 2022-10-22 01:54:47 -0400
• 91cbf56b02 integrate adding stored dac value into rtrunc Peter McGoron 2022-10-22 01:52:58 -0400
• f361cac01b make values update on the start of the control loop, and make resets only take effect after the control loop has completed an iteration Peter McGoron 2022-10-21 17:38:07 -0400
• 12686391ee use integer saturation for dac value adjustment Peter McGoron 2022-10-20 19:43:13 -0400
• 2a300b9438 write total value to dac, not adjustment vlaue Peter McGoron 2022-10-20 15:42:24 -0400
• c42e2fe419 add write-read interface to control loop Peter McGoron 2022-10-18 07:10:06 -0400
• dc2b1fe339 move SPI master out of control loop design Peter McGoron 2022-10-17 14:37:37 -0400
• 0ef00c15d7 move simulators to the same directory of the simulated core Peter McGoron 2022-10-17 00:45:19 -0400
• 029cc53c5f some more changes Peter McGoron 2022-10-17 00:44:30 -0400
• 5125719a1f move control loop stub code to control loop rtl Peter McGoron 2022-10-12 08:48:34 -0400
• 7ca119d45f soc.py legal Peter McGoron 2022-09-17 00:58:15 -0400
• 22ced7dcc8 add SPI link Peter McGoron 2022-09-17 00:37:42 -0400
• e8bbc1303e add readme and COPYING Peter McGoron 2022-09-17 00:35:47 -0400
• 0298299402 add everything im working on Peter McGoron 2022-09-16 18:01:34 -0400
• 7bf784e6bc add jsmn.h Peter McGoron 2022-08-02 19:44:09 -0400
• 2c7ef45254 move tests to remove clutter Peter McGoron 2022-08-02 19:44:04 -0400
• 898b2e8cba ethernet communication Peter McGoron 2022-08-01 14:44:09 -0400
• 7de27a2408 change converter code to drive new verilog Peter McGoron 2022-07-27 09:33:11 -0400
• 1add778b51 change CSR types Peter McGoron 2022-07-27 09:32:49 -0400
• 01cbcb5fae add verilog SPI Peter McGoron 2022-07-21 17:07:52 -0400
• 38c15cec45 add floating point flag to threads Peter McGoron 2022-07-18 12:46:39 -0400
• 52e2dada98 rename dac_adc_test_main.c to test_dac_adc_main.c Peter McGoron 2022-07-15 13:56:58 -0400
• 52ecbd1901 io.c: document ADC code Peter McGoron 2022-07-15 11:01:03 -0400
• 683f85df00 add .gitignore Peter McGoron 2022-07-14 15:48:07 -0400
• 4370ee3d69 add dac_adc test Peter McGoron 2022-07-14 15:47:31 -0400
• 618bf3266a fix io.c includes and logging Peter McGoron 2022-07-14 15:46:59 -0400
• 9a0d590cf1 dont bring in csr locations when not necessary Peter McGoron 2022-07-14 15:46:38 -0400
• ffae5ecdf9 add sign extension, header Peter McGoron 2022-07-14 15:11:22 -0400
• 592939f5bd change pinout Peter McGoron 2022-07-14 15:10:58 -0400
• f6c90ff3d1 ADC code simplification; use lowest common denominator instead Peter McGoron 2022-07-14 10:14:09 -0400
• 75e1001452 checks and misc fix Peter McGoron 2022-07-14 09:27:18 -0400
• 5287366140 start DAC and ADC io Peter McGoron 2022-07-13 15:36:36 -0400
• 32b96eaf9a add macros for number of adcs and dacs Peter McGoron 2022-07-13 15:35:42 -0400
• 60d9b63163 testing PMOD DAC output successful Peter McGoron 2022-07-13 14:12:06 -0400