Commit Graph

328 Commits

Author SHA1 Message Date
Dolu1990 4e7152ae5a IcestormFlow add ultraplus support 2018-05-14 20:18:53 +02:00
Dolu1990 558af595a1 Add ice40 synthesis results 2018-04-26 13:14:37 +02:00
Dolu1990 bdcf3f6234 Add HexTools and add a Briey main which load the ram 2018-04-26 10:27:39 +02:00
Dolu1990 cfc324aa0f Allow csr mtvec to not have reset values 2018-04-24 23:33:48 +02:00
Dolu1990 a9cbc48eb2 PcManagerPlugin is can now handle an external reset vector signal 2018-04-24 23:11:11 +02:00
Dolu1990 c7d852c497 Merge remote-tracking branch 'origin/Wishbone' 2018-04-22 12:15:25 +02:00
Dolu1990 978eb9b6b2 DBusCachedPlugin add CSR info 2018-04-22 11:46:01 +02:00
Dolu1990 74f2a4194a Add ExternalInterruptArrayPlugin 2018-04-20 17:56:21 +02:00
Dolu1990 6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990 455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990 6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990 b37fc3fcc8 Add VexRiscv Wishbone demo for sim (generation ok) 2018-04-18 12:54:20 +02:00
Dolu1990 a66efcb35b Add wishbone support for i$ / d$ (not tested) 2018-04-17 23:56:44 +02:00
Dolu1990 bd4d1eeb01 Update briey soc diagram 2018-03-24 13:49:50 +01:00
Dolu1990 925f6ae811
Update README.md 2018-03-22 15:25:40 +01:00
Dolu1990 cd4ffc2f3f
Update README.md 2018-03-22 15:24:56 +01:00
Dolu1990 7da85303dd
Update README.md 2018-03-22 14:40:08 +01:00
Dolu1990 64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl 2018-03-15 18:56:25 +01:00
Dolu1990 63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings 2018-03-14 00:56:23 +01:00
Dolu1990 d9b7426cde undo InOutWrapper from Murax 2018-03-14 00:47:23 +01:00
Dolu1990 2f8f4d5444 SpinalHDL 1.1.5 2018-03-13 15:45:56 +01:00
Dolu1990 7ea3e24183 update readme perf 2018-03-10 18:37:38 +01:00
Dolu1990 91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) 2018-03-10 13:31:35 +01:00
Dolu1990 f133e69fed fix readme toc 2018-03-10 13:04:48 +01:00
Dolu1990 578e54376a Add MulDivIterativePlugin in readme 2018-03-10 12:57:42 +01:00
Dolu1990 e437a1d44e Add division support in the MulDivInterativePlugin 2018-03-09 22:41:47 +01:00
Dolu1990 36438bd306 iterative mul improvments 2018-03-09 20:00:50 +01:00
Dolu1990 674ab2c594 experimental iterative mul/div combo 2018-03-09 19:07:26 +01:00
Dolu1990 5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990 9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990 53970dd284 SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
2018-03-05 14:34:59 +01:00
Dolu1990 b159ccf8ed
Update README.md 2018-02-27 22:43:53 +01:00
Dolu1990 ccad64def5 Pipeline CSR isWrite 2018-02-26 10:19:33 +01:00
Dolu1990 2b6185b063 Decoding logic : Add primes duplication removal 2018-02-25 08:57:31 +01:00
Dolu1990 2b6f43cef8 Fix Murax memory mapping range 2018-02-25 08:57:31 +01:00
Dolu1990 5260ad5c35 Decoding lib cleaning 2018-02-25 08:57:31 +01:00
Dolu1990 137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values 2018-02-22 22:36:13 +01:00
Dolu1990 d957934949 Fix ICache exception priority over miss reload 2018-02-19 22:44:46 +01:00
Dolu1990 0270ee26fa Merge remote-tracking branch 'origin/reworkInstructionCache' 2018-02-18 23:52:02 +01:00
Dolu1990 8ac4d72623 Update readme 2018-02-18 23:48:20 +01:00
Dolu1990 d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990 93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990 506e0e3f60 New faster/smaller/multi way instruction cache design.
Single or dual stage
2018-02-16 02:21:08 +01:00
Dolu1990 3853e0313b SynthesisBench cleaning/experiments 2018-02-11 14:53:42 +01:00
Dolu1990 2a336c2812 update readme 2018-02-09 00:56:14 +01:00
Dolu1990 0e6ae682b1 Add architecture section describing plugins in the readme 2018-02-09 00:44:27 +01:00
Dolu1990 57ebfee2e6 Add more axi bridges 2018-02-08 21:39:22 +01:00
Dolu1990 fc5d89ad03
Update README.md 2018-02-08 01:07:51 +01:00
Dolu1990 967a0c4caf
Update README.md 2018-02-08 01:01:14 +01:00
Dolu1990 b1bd758fd2
Update README.md 2018-02-08 01:01:01 +01:00