Dolu1990
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42fef8bbcd
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Smp cluster now use i$ reduceBankWidth
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2020-05-12 23:59:38 +02:00 |
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Dolu1990
|
685c914227
|
Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
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2020-05-12 23:59:38 +02:00 |
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Dolu1990
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0471c7ad76
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Fix machineCsr test
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2020-05-12 23:55:47 +02:00 |
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Dolu1990
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cb44a474fc
|
more smp cluster profiling
|
2020-05-12 13:25:55 +02:00 |
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Dolu1990
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63511b19a2
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smp cluster add more profiling
|
2020-05-11 10:35:24 +02:00 |
|
Charles Papon
|
b592b0bff8
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Add regression TRACE_SPORADIC, LINUX_SOC_SMP
regression golden model now properly sync dut exceptions
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2020-05-09 17:00:13 +02:00 |
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Dolu1990
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0a159f06b2
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update smp config
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2020-05-07 22:50:36 +02:00 |
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Dolu1990
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0e76cf9ac8
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i$ now support multi cycle MMU
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2020-05-07 22:50:25 +02:00 |
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Dolu1990
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41ee8fd226
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MmuPlugin now support multiple stages, D$ can now take advantage of that
|
2020-05-07 13:37:53 +02:00 |
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Dolu1990
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8e025aeeaa
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more litex smp cluster pipelining
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2020-05-07 13:18:11 +02:00 |
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Dolu1990
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fc0f3a2020
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cleanup mmu interface
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2020-05-06 18:05:20 +02:00 |
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Dolu1990
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6323caf265
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MMU now allow $ to match tag against tlb pyhsical values directly
D$ retiming
D$ directTlbHit feature added for better timings
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2020-05-06 17:09:46 +02:00 |
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Dolu1990
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ed4a89e4af
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more pipelineing in Litex SMP cluster interconnect
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2020-05-06 17:06:45 +02:00 |
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Dolu1990
|
8043feebd5
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More VexRiscv smp cluster probes
|
2020-05-06 17:06:17 +02:00 |
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Dolu1990
|
09724e907b
|
play around with CSR synthesis impact on design size
|
2020-05-05 00:32:59 +02:00 |
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Dolu1990
|
c16f2ed787
|
Add probes in SmpCluster sim
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2020-05-04 12:54:28 +02:00 |
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Dolu1990
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b0f7f37ac8
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D$ now support memDataWidth > 32
|
2020-05-04 12:54:16 +02:00 |
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Dolu1990
|
93b386e16e
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litex smp cluster now use OO decoder
|
2020-05-02 23:44:58 +02:00 |
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Dolu1990
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f0745eb0d9
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update SMP line size to 64 bytes
|
2020-05-02 23:44:27 +02:00 |
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Dolu1990
|
09ac23b78f
|
Fix SMP fence lock when 4 stages CPU
|
2020-05-01 12:45:16 +02:00 |
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Dolu1990
|
f5f30615ba
|
Got litex SMP cluster to work on FPGA
|
2020-05-01 11:14:52 +02:00 |
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Dolu1990
|
dc0da9662a
|
Update SMP fence (final)
|
2020-05-01 11:14:11 +02:00 |
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Dolu1990
|
7c50fa6d55
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SmpCluster now use i$ line of 64 bytes
|
2020-04-29 14:03:00 +02:00 |
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Dolu1990
|
9e9d28bfa6
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d$ now implement consistancy hazard by using writeback redo
|
2020-04-29 14:02:41 +02:00 |
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Dolu1990
|
86e0cbc1f3
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I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
|
2020-04-29 13:59:43 +02:00 |
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Dolu1990
|
7b80e1fc30
|
Set SMP workspace to use i$ memDataWidth of 128 bits
|
2020-04-28 22:11:41 +02:00 |
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Dolu1990
|
eee9927baf
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IBusCachedPlugin now support memory data width multiple of 32
|
2020-04-28 22:10:56 +02:00 |
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Dolu1990
|
23b8c40cab
|
update travis verilator
|
2020-04-28 16:19:00 +02:00 |
|
Dolu1990
|
03a0445775
|
Fix SMP for configuration without writeback stage.
Include SMP core into the single core tests regressions
|
2020-04-28 15:50:20 +02:00 |
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Dolu1990
|
4a49b23636
|
Fix regression
|
2020-04-28 14:38:27 +02:00 |
|
Dolu1990
|
3ba509931c
|
Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
|
2020-04-27 17:38:06 +02:00 |
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Dolu1990
|
5fd0b220cd
|
CsrPlugin add openSbi config
|
2020-04-27 17:37:30 +02:00 |
|
Dolu1990
|
0c59dd9ed3
|
SMP fence now ensure ordering for all kinds of memory transfers
|
2020-04-27 17:37:15 +02:00 |
|
Dolu1990
|
3fb123a64a
|
fix withStall
|
2020-04-21 21:20:54 +02:00 |
|
Dolu1990
|
3885e52bb7
|
Merge remote-tracking branch 'origin/dev' into smp
|
2020-04-21 17:21:48 +02:00 |
|
Dolu1990
|
4016b1fc52
|
Add sbt assembly
|
2020-04-21 17:18:08 +02:00 |
|
Dolu1990
|
056bf63866
|
Add more consistancy tests
|
2020-04-21 16:03:03 +02:00 |
|
Dolu1990
|
b389878d23
|
Add smp consistency check, fix VexRiscv invalidation read during write hazard logic
|
2020-04-21 12:18:10 +02:00 |
|
Dolu1990
|
0e55caacab
|
deduplicae VexRiscv wishbone
|
2020-04-21 10:33:51 +02:00 |
|
Dolu1990
|
b383b4b98b
|
Add commented usage of fromXilinxBscane2
|
2020-04-20 12:13:12 +02:00 |
|
Dolu1990
|
8e8b64feaa
|
Got full linux / buildroot to boot in 4 cpu config
|
2020-04-19 19:49:26 +02:00 |
|
Dolu1990
|
a1b6353d6b
|
workaround AMO LR/SC consistancy issue, but that need a proper fix
|
2020-04-19 19:48:57 +02:00 |
|
Dolu1990
|
ad2d2e411a
|
Add tap less debug plugin bridges
|
2020-04-19 17:56:33 +02:00 |
|
Dolu1990
|
af128ec9eb
|
revert to 4 cpu
|
2020-04-18 01:27:35 +02:00 |
|
Dolu1990
|
4a49e6d91f
|
initialize the clint in sim
|
2020-04-18 01:26:31 +02:00 |
|
Dolu1990
|
befecc7ed6
|
cleaning
|
2020-04-18 00:51:57 +02:00 |
|
Dolu1990
|
8c0e534c6b
|
Add openSBI test, seem to work fine
|
2020-04-18 00:51:47 +02:00 |
|
Dolu1990
|
ebe070f9dd
|
Update README.md
|
2020-04-17 19:58:54 +02:00 |
|
Dolu1990
|
d5a52caab8
|
fix smp test barrier
|
2020-04-16 17:27:27 +02:00 |
|
Dolu1990
|
d88d04dbc4
|
More SMP tests (barrier via AMO and LRSC)
|
2020-04-16 15:23:25 +02:00 |