Commit Graph

1359 Commits

Author SHA1 Message Date
Dolu1990 fd52f9ba50 Add smp.bin 2020-04-16 02:22:18 +02:00
Dolu1990 73c21177e5 Add VexRiscvSmpCluster, seem to work on simple case 2020-04-16 01:30:03 +02:00
Dolu1990 b9ceabf128 few fixes 2020-04-16 01:29:13 +02:00
Dolu1990 46207abbc4 dataCache now implement invalidation sync 2020-04-16 01:28:38 +02:00
Dolu1990 a00605b10c fix Briey verilator 2020-04-13 13:01:12 +02:00
Dolu1990 467a2bc488 refactor DBus invalidation, and add invalidation enable 2020-04-11 19:06:22 +02:00
Dolu1990 abbfaf6bcf regression : restore normal invalidation setup 2020-04-10 18:58:03 +02:00
Dolu1990 4a9b8c1f72 improve invalidation read during write hazard logic 2020-04-10 14:44:28 +02:00
Dolu1990 0ad0f5ed3f Add d$ invalidation tests
fix d$ invalidation, linux OK
2020-04-10 14:28:16 +02:00
Dolu1990 f71f360e32 Add SMP synthesis 2020-04-10 14:27:39 +02:00
Dolu1990 296cb44bc4 Add hardware AMO support using LR/SC exclusive 2020-04-09 20:12:37 +02:00
Dolu1990 1d0e180e1d Add GenTwoStage config and UltraScale synthesis 2020-04-09 20:11:56 +02:00
Dolu1990 861df664cf clean some AMO stuff 2020-04-08 18:48:01 +02:00
Dolu1990 6922f80a87 DataCache now implement fence operations 2020-04-08 18:12:13 +02:00
Dolu1990 9e1817a280 fix DataCache for config without invalidation 2020-04-07 20:05:24 +02:00
Dolu1990 0c8ea4a368 DataCache add invalidation feature 2020-04-07 19:18:20 +02:00
Dolu1990 1ef099e308 Merge branch 'dev' into smp 2020-04-07 12:29:58 +02:00
Dolu1990 5eaa5ba4db Update README.md 2020-04-07 12:29:40 +02:00
Dolu1990 6e239fb280 Update README.md 2020-04-07 12:29:40 +02:00
Dolu1990 f20eb4d541 Merge pull request #115 from antmicro/fix_emulator
emulator: Use external hw/common.h from LiteX
2020-04-07 12:29:40 +02:00
Dolu1990 ddc59bc404 Fix DebugPlugin step by step 2020-04-07 12:27:52 +02:00
Dolu1990 5aa0b86d96 Fix DebugPlugin step by step 2020-04-07 12:13:40 +02:00
Dolu1990 a52b833727 fix weird regression testbench memory bug 2020-04-06 21:42:44 +02:00
Dolu1990 a107e45116 fix non smp regression 2020-04-06 06:43:28 +02:00
Dolu1990 ca72a421be LrSc align software model to the hardware. Linux OK 2020-04-05 21:45:45 +02:00
Dolu1990 2eec18de65 LrSc SMP, linux crash in userspace 2020-04-05 16:28:46 +02:00
Dolu1990 f2ef8e95ab Implement external LrSc 2020-04-05 11:38:57 +02:00
Dolu1990 ff074459ad Fix LrSc for configs without mmu 2020-04-04 22:54:35 +02:00
Dolu1990 c9bbf0d12a update LrSc reservation logic to match the spec 2020-04-04 21:21:35 +02:00
Dolu1990 31d2aaa05b
Update README.md 2020-03-28 15:38:32 +01:00
Dolu1990 2dac7dae32 Fix BranchPlugin.jumpInterface priority to avoid conflicts with other instructions on DYNAMIC_TARGET missprediction 2020-03-28 14:36:06 +01:00
Dolu1990 b3215e8beb Make things generated in a deterministic order 2020-03-24 13:11:07 +01:00
Dolu1990 31667b18d8
Update README.md 2020-03-20 11:26:38 +01:00
Dolu1990 97258c214a
Merge pull request #115 from antmicro/fix_emulator
emulator: Use external hw/common.h from LiteX
2020-03-18 12:02:27 +01:00
Dolu1990 c122365a52 Smp spec update, add Interface subsets (writeOnly, readOnly) 2020-03-11 14:20:13 +01:00
Dolu1990 95237b23ea SpinalHDL 1.4.0
Merge branch 'dev'
2020-03-09 13:49:06 +01:00
Dolu1990 ab2f4cd2b7 Merge branch 'master' into dev
# Conflicts:
#	README.md
#	build.sbt
2020-03-09 13:41:23 +01:00
Dolu1990 5f90702b2f SpinalHDL update 2020-03-09 13:14:16 +01:00
Dolu1990 defe3c5558 DataCache relax flush timings 2020-03-08 12:35:24 +01:00
Dolu1990 04bf1a4ced Fix build.sbt 2020-03-08 00:23:19 +01:00
Dolu1990 7a5afb86a5 Fix build.sbt 2020-03-07 19:09:33 +01:00
Dolu1990 97db4f02a0 Merge branch 'rework_fetch' into dev 2020-03-07 18:22:46 +01:00
Dolu1990 44005ebf31 update Synthesis results 2020-03-07 18:22:01 +01:00
Charles Papon 2c6076ba97 improve smp spec 2020-03-07 13:35:21 +01:00
Charles Papon b7ae902bbc smp spec improvements, no more read abort 2020-03-05 00:14:11 +01:00
Charles Papon 58af94269e add CsrPlugin.csrOhDecoder 2020-03-05 00:13:04 +01:00
Charles Papon 50ec0a1917 update readme perf 2020-03-05 00:12:46 +01:00
Charles Papon 505d0b700a MulDivPlugin now give names to div stages 2020-03-04 19:58:54 +01:00
Dolu1990 0a212c91fd update synthesisBench paths 2020-03-04 18:13:56 +01:00
Dolu1990 ff5cfc0dde Fix DebugPlugin step 2020-03-03 18:27:53 +01:00