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VexRiscv
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1064 Commits

Author SHA1 Message Date
Dolu1990 f872d599e2 Add decodePcGen 2018-03-20 18:34:36 +01:00
Dolu1990 1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction 2018-03-20 00:01:28 +01:00
Dolu1990 ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework 2018-03-18 13:21:21 +01:00
Dolu1990 64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl 2018-03-15 18:56:25 +01:00
Dolu1990 63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings 2018-03-14 00:56:23 +01:00
Dolu1990 d9b7426cde undo InOutWrapper from Murax 2018-03-14 00:47:23 +01:00
Dolu1990 2f8f4d5444 SpinalHDL 1.1.5 2018-03-13 15:45:56 +01:00
Dolu1990 7ea3e24183 update readme perf 2018-03-10 18:37:38 +01:00
Dolu1990 91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) 2018-03-10 13:31:35 +01:00
Dolu1990 f133e69fed fix readme toc 2018-03-10 13:04:48 +01:00
Dolu1990 578e54376a Add MulDivIterativePlugin in readme 2018-03-10 12:57:42 +01:00
Dolu1990 e437a1d44e Add division support in the MulDivInterativePlugin 2018-03-09 22:41:47 +01:00
Dolu1990 36438bd306 iterative mul improvments 2018-03-09 20:00:50 +01:00
Dolu1990 674ab2c594 experimental iterative mul/div combo 2018-03-09 19:07:26 +01:00
Dolu1990 5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990 9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990 53970dd284 SpinalHDL 1.1.4 
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
 2018-03-05 14:34:59 +01:00
Dolu1990 b159ccf8ed
Update README.md 2018-02-27 22:43:53 +01:00
Dolu1990 ccad64def5 Pipeline CSR isWrite 2018-02-26 10:19:33 +01:00
Dolu1990 2b6185b063 Decoding logic : Add primes duplication removal 2018-02-25 08:57:31 +01:00
Dolu1990 2b6f43cef8 Fix Murax memory mapping range 2018-02-25 08:57:31 +01:00
Dolu1990 5260ad5c35 Decoding lib cleaning 2018-02-25 08:57:31 +01:00
Dolu1990 137b1ee32c Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values 2018-02-22 22:36:13 +01:00
Dolu1990 d957934949 Fix ICache exception priority over miss reload 2018-02-19 22:44:46 +01:00
Dolu1990 0270ee26fa Merge remote-tracking branch 'origin/reworkInstructionCache' 2018-02-18 23:52:02 +01:00
Dolu1990 8ac4d72623 Update readme 2018-02-18 23:48:20 +01:00
Dolu1990 d0e963559a Update readme with the new ICache implementation 2018-02-18 23:48:11 +01:00
Dolu1990 93110d3b95 Add jump priority managment in PcPlugins 2018-02-16 14:27:20 +01:00
Dolu1990 506e0e3f60 New faster/smaller/multi way instruction cache design. 
Single or dual stage
 2018-02-16 02:21:08 +01:00
Dolu1990 3853e0313b SynthesisBench cleaning/experiments 2018-02-11 14:53:42 +01:00
Dolu1990 2a336c2812 update readme 2018-02-09 00:56:14 +01:00
Dolu1990 0e6ae682b1 Add architecture section describing plugins in the readme 2018-02-09 00:44:27 +01:00
Dolu1990 57ebfee2e6 Add more axi bridges 2018-02-08 21:39:22 +01:00
Dolu1990 fc5d89ad03
Update README.md 2018-02-08 01:07:51 +01:00
Dolu1990 967a0c4caf
Update README.md 2018-02-08 01:01:14 +01:00
Dolu1990 b1bd758fd2
Update README.md 2018-02-08 01:01:01 +01:00
Dolu1990 3ee111e100 Update readme (gcc stuff) 2018-02-05 16:34:10 +01:00
Dolu1990 d4b05ea365 Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location 
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
 2018-02-05 16:16:27 +01:00
Dolu1990 4729e46763 Add DummyFencePlugin 2018-02-03 12:28:53 +01:00
Dolu1990 0bc3a1a314
Update README.md 2018-02-02 17:18:47 +01:00
Dolu1990 3d97c1f2f2
Update README.md 2018-02-02 14:47:07 +01:00
Dolu1990 f13dba847c Add custom csr gpio example 2018-02-02 11:14:55 +01:00
Dolu1990 b7d8ed8a81 Add onWrite/onRead/isWriting/isReading on the CsrPlugin 2018-02-01 21:28:28 +01:00
Dolu1990 4ee2482cbf Fix custom_csr regression against random ibus stall 2018-01-31 18:33:21 +01:00
Dolu1990 d2e5755df4 revert removed code by mistake 2018-01-31 18:29:30 +01:00
Dolu1990 30b05eaf96 Add CsrInterface to allow custom CSR addition 
Add CustomCsrDemoPlugin as a show case
 2018-01-31 18:13:42 +01:00
Dolu1990 42e677ec0d 1.40 DMIPS/Mhz update 2018-01-29 15:24:14 +01:00
Dolu1990 bdbf6ecf17 BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions 2018-01-29 14:52:31 +01:00
Dolu1990 0d318ab6b9 Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz) 
Add longer timeouts in the regressions tests
 2018-01-29 13:17:11 +01:00
Dolu1990 307c0b6bfa Now mret and ebreak are only allowed in CSR machine mode 2018-01-28 16:34:55 +01:00