Charles Papon
|
926b74a203
|
shorter coremark
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2019-04-10 15:41:58 +02:00 |
|
Charles Papon
|
189cadfbb3
|
Add coremark
|
2019-04-10 15:41:38 +02:00 |
|
Charles Papon
|
d7f6c18c0a
|
Fix DebugPlugin -> force machine mode, force uncached memory load
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2019-04-10 00:35:15 +02:00 |
|
Charles Papon
|
9b6b65b8b4
|
Fix icache test when dynamic target branch prediction is enabled
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2019-04-09 19:37:18 +02:00 |
|
Charles Papon
|
a6dc530441
|
Added lrsc/amo tests
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2019-04-09 19:27:42 +02:00 |
|
Charles Papon
|
fd42e7701e
|
Add hardware AMO, require AMO=yes in sim and withAmo=true in linux.scala
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2019-04-09 01:22:32 +02:00 |
|
Charles Papon
|
21cb8615fd
|
Clean and fix things to get all the non-linux configs and machine only configs working
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2019-04-08 16:06:05 +02:00 |
|
Charles Papon
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32921491b8
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#60 Fix instruction cache refill
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2019-04-08 14:24:37 +02:00 |
|
Charles Papon
|
fd15a938c5
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#60 Fix machine mode emulator atomic emulation. Do not write regfile if the page was set as read only.
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2019-04-08 13:20:56 +02:00 |
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Charles Papon
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c2595273ec
|
Add a busy flag from MMU ports
iBus/dBus now halt on MMU busy, which avoid looping forever on page fault
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2019-04-08 11:38:40 +02:00 |
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Charles Papon
|
f89ee0d422
|
#60 Fix MMU holding invalid tlb, while linux is assuming it isn't doing so.
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2019-04-07 15:44:25 +02:00 |
Tom Verbeure
|
4fd36454d7
|
Complain about wrong earlyBranch settings.
|
2019-04-06 12:58:19 -07:00 |
|
Tom Verbeure
|
39a4aa5e26
|
GenMicroNoCsr: no memory stage, no write-back stage
|
2019-04-06 12:38:54 -07:00 |
|
Charles Papon
|
ffafc27104
|
Merge branch 'linuxDev' into linux
|
2019-04-06 02:01:08 +02:00 |
|
Charles Papon
|
6df3e57843
|
workaround Verilator comparaison linting
|
2019-04-06 02:00:47 +02:00 |
|
Charles Papon
|
21b4ae8f2f
|
update todo, nothing todo ? everything done ?
|
2019-04-06 01:42:01 +02:00 |
|
Charles Papon
|
e7f3dd5553
|
Rework CsrPlugin exception delegation
|
2019-04-05 23:40:39 +02:00 |
|
Charles Papon
|
ddf0f06834
|
Add more delegation tests
Reduce dcache test duration
|
2019-04-05 22:56:12 +02:00 |
|
Charles Papon
|
acaa931e11
|
Rework CsrPlugin interrupt delegation
|
2019-04-05 22:55:42 +02:00 |
|
Charles Papon
|
9e72971ff0
|
Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin
SUM was in fact already supported
|
2019-04-05 21:34:44 +02:00 |
|
Charles Papon
|
82c894932a
|
update todolist
|
2019-04-05 20:04:28 +02:00 |
|
Charles Papon
|
aeb418a99e
|
Add dcache tests
|
2019-04-05 20:03:22 +02:00 |
|
Charles Papon
|
5a6665e57f
|
Fix DataCache flush on the last line
|
2019-04-05 20:02:57 +02:00 |
|
Charles Papon
|
8459d423b8
|
add icache flush test
|
2019-04-05 18:11:33 +02:00 |
|
Charles Papon
|
60a41bfc75
|
rework i$ flush
|
2019-04-05 18:11:10 +02:00 |
|
Charles Papon
|
f5d4e745c7
|
Look like precise fence.i isn't required in practice
|
2019-04-05 18:08:25 +02:00 |
|
Charles Papon
|
446e9625af
|
Centralised all todo in linux.scala
Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
|
2019-04-05 12:17:29 +02:00 |
|
Charles Papon
|
888e1c0b8a
|
Fix RVC instruction cache xtval allignement
|
2019-04-05 01:08:57 +02:00 |
|
Charles Papon
|
8e6010fd71
|
Got the debug plugin working with the linux config (had to disable CSR ebreak)
|
2019-04-05 00:25:27 +02:00 |
|
Charles Papon
|
4f0a02594c
|
Change LR/SC to reserve the whole memory
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
|
2019-04-04 20:34:35 +02:00 |
|
Charles Papon
|
f8b438d9dc
|
cleaning
|
2019-04-04 12:59:08 +02:00 |
|
Charles Papon
|
de1c9c6fea
|
Removing D$ reports
|
2019-04-03 14:47:00 +02:00 |
|
Charles Papon
|
3f7a859e07
|
Got multiway I$ D$ running linux fine.
|
2019-04-03 14:33:35 +02:00 |
|
Charles Papon
|
922c18ee49
|
Add data cache flush feature
|
2019-04-03 15:56:58 +02:00 |
|
Charles Papon
|
066f562c5e
|
Got the MMU refilling itself with datacache cached memory access instead of io accesses
|
2019-04-03 14:32:21 +02:00 |
|
Charles Papon
|
8be40e637b
|
#60 Got the new data cache design passing all tests and running linux
|
2019-04-02 23:44:53 +02:00 |
|
Charles Papon
|
fd4da77084
|
#60 Got the new instruction cache design passing the standard regressions
|
2019-04-02 00:26:53 +02:00 |
|
Charles Papon
|
bc0af02c97
|
#60 Got instruction cache running linux :D
|
2019-04-01 11:59:04 +02:00 |
|
Charles Papon
|
1dff9aff8a
|
#60 Fix interrupt causing fetch privilege issues
|
2019-04-01 10:47:54 +02:00 |
|
Charles Papon
|
e74a5a71eb
|
Better simulation console integration
|
2019-04-01 10:31:55 +02:00 |
|
Charles Papon
|
369a3d0f5f
|
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
|
2019-03-31 23:43:56 +02:00 |
|
Charles Papon
|
c7314cc606
|
Got buildroot login, userspace, commands working
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
|
2019-03-31 15:17:45 +02:00 |
|
Dolu1990
|
de500ad8f9
|
Add qemu command
|
2019-03-30 18:29:17 +01:00 |
|
Dolu1990
|
9383445e0b
|
Add a qemu option (wip)
|
2019-03-30 18:26:44 +01:00 |
|
Charles Papon
|
1a36f2689d
|
#60 Fix software model. Forgot physical address for on RVC instruction
|
2019-03-30 11:24:29 +01:00 |
|
Charles Papon
|
29980016f3
|
#60 Fix instruction fetch exception PC by forcing LSB to be zero
|
2019-03-30 10:10:25 +01:00 |
|
Dolu1990
|
9fff419346
|
Better fix
|
2019-03-29 09:18:44 +01:00 |
|
Dolu1990
|
391cff69d3
|
#60 should fix the first instruction fetch privilege after interrupt
|
2019-03-29 09:02:44 +01:00 |
|
Dolu1990
|
0c48729611
|
Sync impact less changes (asfar i know)
|
2019-03-29 08:43:15 +01:00 |
|
Dolu1990
|
ad27007c3c
|
DBusSimplePlugin AHB bridge add hazard checking, pass tests
|
2019-03-28 11:41:49 +01:00 |