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VexRiscv
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413 Commits

Author SHA1 Message Date
Tom Verbeure ea62fd0e16 Same thing for DBusSimpleBus. 2019-03-23 23:36:13 +00:00
Tom Verbeure 95c3e436dc Make toPipelinedMemoryBus() just like the other busses 2019-03-23 22:32:48 +00:00
Tom Verbeure b63395435f SimpleMul core. 2019-03-16 15:44:18 +00:00
Tom Verbeure 5bc53c08ce Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv into MulSimple 2019-03-16 15:39:07 +00:00
Dolu1990 9a61ff8347 Merge remote-tracking branch 'origin/dev' 2019-03-10 11:14:09 +01:00
Dolu1990 bad60f39cd Fix Decoding benchmark 2019-03-10 11:12:32 +01:00
Dolu1990 434793711b fix part of #59 2019-02-26 17:26:42 +01:00
Dolu1990 e0c8ac01d2 Add custom external interrupts 2019-02-03 15:20:34 +01:00
Dolu1990 11f55359c6 IBusCache can now avoid injectorStage in singleStage mode 2019-01-30 01:37:47 +01:00
Dolu1990 56e3321394 cpp regresion now print the time of failure 2019-01-30 01:36:24 +01:00
Dolu1990 f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990 b5caca54cd restore all feature in TestsWorkspace 2019-01-16 15:25:50 +01:00
Dolu1990 927ab6d127 Merge remote-tracking branch 'origin/master' into dev 2018-12-30 15:53:25 +01:00
Dolu1990 dd42e30c61 Merge remote-tracking branch 'origin/master' into dev 2018-12-29 14:04:07 +01:00
Dolu1990 d617bafb08 Roll back VexRiscvAvalonForSim to use caches 2018-12-25 00:15:23 +01:00
Brett Foster 961abb3cf1 Avalon: Debug Clock Domain for JTAG 
This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.

See SpinalHDL/VexRiscv#48
 2018-12-22 07:58:59 -08:00
Dolu1990 76ebfb2243 Fix machine mode to supervisor delegation 2018-12-10 13:15:03 +01:00
Dolu1990 d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990 281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990 1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990 f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990 9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990 52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990 68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990 eca54585b0 Fix hardware breakpoint 2018-12-04 16:57:24 +01:00
Dolu1990 ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990 3d71045159 DebugPlugin doesn't require memory/writeback stage anymore 2018-12-01 18:24:33 +01:00
Dolu1990 58d7a4784d move HexTools into SpinalHDL lib 2018-11-30 17:39:33 +01:00
Dolu1990 b1b7da4f10 Rename SimpleBus into PipelinedMemoryBus 
Move PipelinedMemoryBus into SpinalHDL lib
 2018-11-30 17:37:17 +01:00
Dolu1990 2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990 7075e08d9f Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage 2018-11-24 13:38:54 +01:00
Dolu1990 c2b9544794 Allow iBusCached plugin to be used when no memory stage is present 2018-11-24 13:37:53 +01:00
Dolu1990 0086de9e36 Fix CsrPlugin catch illegalAccess 
Add dhrystone optimized divider
cleaning
 2018-11-20 19:39:17 +01:00
Dolu1990 75d4d049d7 Add shadow regfile 
various cleaning
 2018-11-16 17:06:11 +01:00
Dolu1990 cc48fc7403 add fenceiGenAsANop 2018-11-13 15:17:35 +01:00
Dolu1990 0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990 fb9ea11a5e Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE) 2018-11-09 05:41:43 +01:00
Dolu1990 b12e15b112 branch/csr/muldiv minor improvments 2018-11-07 19:27:49 +01:00
Dolu1990 b7f3ee5e06 Fix CsrPlugin pipelined option 2018-11-05 16:22:41 +01:00
Dolu1990 662d76e3aa csrPlugin : avoid using ALU to get SRC1 (which was useless) 2018-11-03 11:29:30 +01:00
Dolu1990 978232fd63 Optimise div iterative plugin done signal 2018-11-03 11:12:37 +01:00
Dolu1990 c8ac214097 Optimize CSR 2018-10-28 02:18:27 +02:00
Dolu1990 51de2b5820 SimpleBusInterconnect now adapte address width 2018-10-28 02:18:08 +02:00
Dolu1990 00bf84b7f8 Add SimpleBusInterconnect 2018-10-25 23:47:05 +02:00
Dolu1990 4ed4af6a3e SrcPlugin add decodeAddSub option 2018-10-24 01:28:37 +02:00
Dolu1990 372063582c Improve CsrPlugin CombinatorialPaths 2018-10-23 19:07:08 +02:00
Dolu1990 7096c63d50 Add more SimpleBus utilies 2018-10-23 17:46:31 +02:00
Dolu1990 7c0f2dc713 Add SimpleBus object 2018-10-20 12:39:30 +02:00
Morard Dany 85e696b286 CsrPlugin : Add mtvecModeGen 2018-10-16 14:53:41 +02:00
Dolu1990 905abd5aaa Add wfiGenAsWait and wfiGenAsNop 
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
 2018-10-16 13:07:30 +02:00