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VexRiscv
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413 Commits

Author SHA1 Message Date
Dolu1990 f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990 2b29690010 Clean branch plugin lsb bit calculation 
BranchPlugin doesn't try anymore to catch exception when RVC is on
 2018-10-12 12:24:52 +02:00
Dolu1990 eea92154ae fetcher force PC LSB to be zero 2018-10-12 12:02:52 +02:00
Dolu1990 0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990 594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990 8c25e73b9d Fix DIV negative values divided by zero 2018-10-11 22:18:21 +02:00
Dolu1990 c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990 8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990 40d85b8c70 Add fenceiGenAsAJump into BranchPlugin 2018-10-10 21:13:21 +02:00
Dolu1990 68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990 0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990 48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990 c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990 0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990 65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00
Dolu1990 7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990 39c6bc11d6 Pass basic regression again 2018-09-29 19:04:20 +02:00
Dolu1990 5ad7c39f47 wip 2018-09-29 12:04:58 +02:00
Dolu1990 37a1970ad6 wip 2018-09-28 16:02:33 +02:00
Dolu1990 9a3510f63d Map all supervisor registers 2018-09-27 19:03:57 +02:00
Dolu1990 acd1ca422a wip 2018-09-27 18:24:40 +02:00
Dolu1990 6dde73f97c Murax demo with XIP is now fully defined in SpinalHDL 2018-09-27 00:55:30 +02:00
Dolu1990 aff436ddcf Sync with SpinalHDL head 
Add mmu test into the dhrystone regression command
 2018-09-24 18:31:33 +02:00
Dolu1990 1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990 86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990 56fd73fbbc Add missing bin files 2018-09-23 19:26:11 +02:00
Dolu1990 bdc3246f5a Fix xip gitignore 2018-09-23 19:23:43 +02:00
Dolu1990 5024cc5616 Hardware breakpoint feature added 
Murax XIP debugging passed tests
 2018-09-20 13:11:20 +02:00
Dolu1990 ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990 b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990 3e17461cc7 Add optional XIP to Murax 2018-09-16 11:00:56 +02:00
Dolu1990 d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990 791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00
Dolu1990 0255f51cc5 Add unpipelined Wishbone support for uncached version 2018-08-24 16:41:34 +02:00
Dolu1990 7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990 38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00
Dolu1990 dca1e5f438 revert RVC from murax 2018-08-17 23:12:45 +02:00
Dolu1990 8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	README.md
	src/main/scala/vexriscv/TestsWorkspace.scala
	src/test/scala/vexriscv/Play.scala
 2018-08-17 20:56:51 +02:00
Dolu1990 9c7e089329 Fix ExternalInterruptArrayPlugin CSR ids 2018-08-17 20:38:33 +02:00
Dolu1990 1d3ac7830b restore tests without CSR catch all 2018-08-17 19:33:41 +02:00
Dolu1990 330ee14a23 final fetchRework commit ? 2018-08-17 19:13:23 +02:00
Dolu1990 91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue 2018-08-14 11:51:53 +02:00
Tom Verbeure ae85698a2b MulSimple 2018-08-09 22:15:26 -07:00
Dolu1990 32fe1dcbd4 Add google cloud VM regressions scripts 2018-07-07 21:47:09 +02:00
Dolu1990 3ea4f28354 wip 2018-07-07 11:39:42 +02:00
Dolu1990 9c1a8ea219 Fix EPC 
Fix Freertos binaries
wip
 2018-07-03 23:17:32 +02:00
Dolu1990 ffe5fa23f0 wip 2018-06-25 09:36:07 +02:00
Dolu1990 d73aa9ce00 rework csr exception/interrupt handeling wip 2018-06-24 00:14:55 +02:00
Dolu1990 dd47db9ad0 wip 2018-06-20 12:35:12 +02:00
Dolu1990 8886f7e6d4 test wip 2018-06-19 16:15:42 +02:00
Dolu1990 1090111a6f TestIndividual is now fully random 2018-06-15 13:00:59 +02:00
Dolu1990 b2cd8c5314 Fix exception pipelining 2018-06-15 13:00:26 +02:00
Dolu1990 83864710a3 Fix IBusCached single cycle interaction with mmu bus 
Add random test configs
 2018-06-09 08:40:19 +02:00
Dolu1990 08a1212fca Add DBus simple/cached regressions 2018-06-07 02:31:18 +02:00
Dolu1990 6bc5431fcd Add iBusCached regressions 2018-06-07 00:57:26 +02:00
Dolu1990 5e7dd02bf7 Fix relaxedPc/DYNAMIC_TARGET interaction 2018-06-06 18:30:30 +02:00
Dolu1990 dc968020c4 Fix relaxedBusCmdValid pendingCmd overflow 2018-06-06 15:20:37 +02:00
Dolu1990 7768f065e4 Add many cpu configs on regressions tests (some config are broken) 2018-06-06 02:23:07 +02:00
Dolu1990 8729530a8d Fix Dynamicfetch/!rvc config 2018-06-05 02:33:18 +02:00
Dolu1990 930563291c Allow RVC/dynamic_target/fetch bus latency > 1 all together 
Fix freeretos rvc regressions
 2018-06-05 02:21:05 +02:00
Dolu1990 702db29edd Fix dynamic prediction RVC allignement 2018-06-04 20:03:08 +02:00
Dolu1990 fc835f370e Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function 2018-06-04 19:45:15 +02:00
Tom Verbeure 52f1cdbca7 Fix some missing Barriel -> barriel fixes 2018-06-03 21:46:40 -07:00
Dolu1990 9f0387350b Add Freertos RVC binaries regression 2018-06-03 17:10:58 +02:00
Tom Verbeure e9bbbb3965 BarrielShifter -> BarrelShifter 2018-06-03 07:40:11 +00:00
Dolu1990 7375855e58 DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch) 2018-06-03 00:50:18 +02:00
Dolu1990 98b68093f4 dynamic_prediction + RVC => instruction fetch stopped midair 2018-05-28 21:28:39 +02:00
Dolu1990 863ac3f34d dynamic prediction now use history from first aligned word of the instruction instead of the last one. 2018-05-28 11:03:13 +02:00
Dolu1990 8a0c238bf3 dynamic prediction ok with rvc, todo dynamic_target with rvc 2018-05-28 10:59:22 +02:00
Tom Verbeure 0335543309 More Unrolls 2018-05-28 07:20:26 +00:00
Tom Verbeure 1613191779 Unrool -> Unroll 2018-05-28 07:18:13 +00:00
Dolu1990 7493e70265 Merge remote-tracking branch 'origin/master' into reworkFetcher 2018-05-28 09:02:30 +02:00
Dolu1990 5943ee727e Fill travis, DhrystoneBench is now a Unit test 2018-05-28 09:02:01 +02:00
Dolu1990 1752b5f184 Give name to inter stages registers 2018-05-27 23:39:49 +02:00
Dolu1990 5704f22739 wip 2018-05-27 23:33:57 +02:00
Dolu1990 346338f084 Better HexTools 2018-05-26 11:51:42 +02:00
Dolu1990 6142b04603 Move HexTools into Spinal 2018-05-26 11:43:16 +02:00
Dolu1990 c8677cca9b Better HexTools 2018-05-26 11:32:36 +02:00
Dolu1990 b0777bc646 Merge remote-tracking branch 'origin/master' into reworkFetcher 2018-05-24 14:05:35 +02:00
Dolu1990 6004dcc365 Fix typo 2018-05-24 14:04:50 +02:00
Dolu1990 9815763b7f Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
	src/test/cpp/regression/main.cpp
 2018-05-24 14:04:01 +02:00
Dolu1990 c4f33b30e2 Update SynthesisBench murax 2018-05-24 14:03:28 +02:00
Dolu1990 485f35a1b5 IBusCachedPlugin default is two cycle cache with single cycle ram. 2018-05-24 13:46:31 +02:00
Dolu1990 2f8ccc55b6 Fix branch plugin decode prediction exception by using the instruction decoder 2018-05-24 12:52:00 +02:00
Dolu1990 a53f8fdc35 Clean configs 2018-05-23 16:57:32 +02:00
Dolu1990 eb5bc4a791 Fix RVC decompressor (ALU immediats) 2018-05-22 17:23:20 +02:00
Dolu1990 ff760a0bf0 DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS) 2018-05-21 13:45:08 +02:00
Dolu1990 7ffbfab312 Reintroduce MMU feature (pass tests) 2018-05-16 20:32:12 +02:00
Dolu1990 c8cec59f1d Update IBusCachedPlugin parameters 2018-05-16 12:11:53 +02:00
Dolu1990 3b54ecf303 Restore two cycle instruction cache features 2018-05-15 23:03:33 +02:00
Dolu1990 4e7152ae5a IcestormFlow add ultraplus support 2018-05-14 20:18:53 +02:00
Dolu1990 df3d9ccb13 rework IBusSimplePlugin parameters 2018-05-14 10:31:40 +02:00
Dolu1990 c0271d382f More assertion (csrPlugin) 2018-05-14 10:13:44 +02:00
Dolu1990 9caa7163ae IBusSimplePlugin add relaxedBusCmdValid feature 2018-05-14 10:04:19 +02:00
Dolu1990 610bd01f3b remove rspStageGen 2018-05-14 09:21:28 +02:00
Dolu1990 7b37669a0f Add exception catch to iBusSimplePLugin (pass) 2018-05-09 18:43:48 +02:00
Dolu1990 acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990 0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990 e65757e34c wip before moving the fetchHalt 2018-05-06 16:38:00 +02:00
Dolu1990 294293cb70 Reintroduce debug plugin (instruction injector need optimisations) 2018-05-05 23:05:32 +02:00