50ec0a1917
update readme perf
2020-03-05 00:12:46 +01:00
505d0b700a
MulDivPlugin now give names to div stages
2020-03-04 19:58:54 +01:00
0a212c91fd
update synthesisBench paths
2020-03-04 18:13:56 +01:00
ff5cfc0dde
Fix DebugPlugin step
2020-03-03 18:27:53 +01:00
12463e40a4
improve debugPlugin step logic
2020-03-03 15:59:30 +01:00
fd37962a58
typo
2020-03-03 10:56:12 +01:00
ef5398ce21
Fix #117 DataCache mem blackboxing
2020-03-02 14:24:27 +01:00
54581f6d9e
Fix #117 DataCache mem blackboxing
2020-03-02 14:23:59 +01:00
78d4660282
Merge branch 'dev' into rework_fetch
...
# Conflicts:
# src/test/scala/vexriscv/TestIndividualFeatures.scala
2020-03-01 22:58:25 +01:00
ea5464ea26
TestIndividualFeatures is now multithreaded
2020-03-01 21:40:53 +01:00
02545b9bea
typo
2020-03-01 13:03:40 +01:00
559260020b
Improve testing infrastructure with more options and better readme
...
https://github.com/litex-hub/linux-on-litex-vexriscv/issues/112
2020-03-01 13:02:08 +01:00
0c7556ad7f
Update README.md
2020-02-29 23:46:21 +01:00
25d880f6c7
Fix synthesis bench
2020-02-28 18:20:08 +01:00
c94d8f1c6c
Fetcher and IBusSimplePlugin flush reworked
2020-02-28 17:23:44 +01:00
492310e6fa
DBusCachedPlugin fix noWriteBack redo priority
2020-02-28 17:21:59 +01:00
76d063f20a
Fix MulPlugin keep attribute
2020-02-24 22:43:08 +01:00
f88b259eba
emulator: Use external hw/common.h from LiteX
...
Remove code copied from `hw/common.h` and use
the header from the LiteX repository provided
using `LITEX_BASE` environment variable.
Content of `common.h` is now evolving (new functions
are added, some are removed) and syncing it
between repos would be cumbersome.
2020-02-24 14:27:45 +01:00
999a868c14
Update readme VexRiscv perf numbers
2020-02-24 00:07:14 +01:00
485b4a5838
Improve maxPerf configs
2020-02-23 23:52:43 +01:00
fad09e805f
Add Fetcher.predictionBuffer option to pipeline BRANCH_TARGET, higher FMax, about 1 ns critical path gain on Arty7 => 5 ns
2020-02-23 23:18:27 +01:00
67d2071a32
typo
2020-02-23 23:17:02 +01:00
c8016e90a4
MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP
2020-02-23 20:25:31 +01:00
01e5112680
Fetcher RVC ensure redo keep PC(1)
...
Fix BranchTarget RVC inibition
2020-02-23 10:44:44 +01:00
5ea0b57d1b
Fix BRANCH_TARGET with RVC patch
2020-02-22 11:53:47 +01:00
41008551c1
CsrPlugin redo interface do not need next pc calculation
2020-02-21 20:01:35 +01:00
4ad1215873
Fix iBusSimplePlugin MMU integration
2020-02-21 13:28:42 +01:00
befc54a444
No more Fetcher flush() API as it can now be done via the decoder.flushNext
2020-02-21 13:28:29 +01:00
32fade50e5
Fix fetcher decompressor when driving decode stage
2020-02-21 02:03:29 +01:00
59508d5b57
Fix target branch prediction for RVC, all default configs pass dhrystone
2020-02-20 02:27:57 +01:00
a684d5e4d1
Rework/clean decompressor logic
2020-02-19 01:20:52 +01:00
a7440426fd
Fix FetchPlugin redo gen condition
...
Fix injectorFailure reset
2020-02-18 01:00:11 +01:00
f63c4db469
Fix CsrPlugin pipeline liberator
2020-02-18 00:59:39 +01:00
53a29e35e9
fix deleg external interrupt propagation time failure
2020-02-17 23:27:17 +01:00
e0cd9a6e06
clean iBusRsp redo
2020-02-17 22:45:34 +01:00
0e0a568743
Apply DYNAMIC_TARGET correction all the time
2020-02-17 21:43:02 +01:00
e23295f06e
Fix Fetcher pcValid pipeline
2020-02-17 19:29:41 +01:00
9e75e2cb58
IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction.
...
Fix some fetch flush
DYNAMIC_PREDICTION start to work again
2020-02-17 14:36:08 +01:00
8be50b8e3d
IBusFetcher now support proper iBusRsp.redo/flush
2020-02-17 12:50:12 +01:00
ebfa9e6577
Merge branch 'dev' into rework_fetch
2020-02-16 18:52:31 +01:00
29f85a7ae2
Remove INSTRUCTION_READY
...
Add proper Fetcher.ibusRsp.flush
prediction are disabled yet
much is broken for sure, WIP
2020-02-16 18:44:10 +01:00
0c255e2404
Merge branch 'compiler_plugin' into dev
2020-02-16 14:34:26 +01:00
3d34d754a9
Remove usages of implicit string to B/U/S
2020-02-15 10:11:00 +01:00
d241f35625
Remove usages of implicit string to B/U/S
2020-02-15 10:10:04 +01:00
f1959ff830
smp spec typo
2020-02-15 00:26:11 +01:00
6edab1eb34
Add SMP spec draft
2020-02-15 00:24:33 +01:00
b728b60051
Merge pull request #113 from japm48/patch-2
...
Murax on arty_a7: fix inferred memory type
2020-02-12 23:27:51 +01:00
6547eefffd
Murax on arty_a7: fix mkdir error
2020-02-11 18:58:43 +01:00
ecee7122a5
Merge pull request #112 from japm48/patch-1
...
Readme: fix spelling and made some clarifications
2020-02-11 18:51:45 +01:00
163611bd11
Murax on arty_a7: fix RAMB type on soc_mmi.tcl
2020-02-11 18:49:56 +01:00
Charles Papon
Mateusz Holenko
japm48