Dolu1990
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a6e89fe05c
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fpu vex regression goldenModel can now assert FPU interface
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2021-02-19 17:55:56 +01:00 |
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Dolu1990
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3f226b758c
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fpu fix exception flag handeling
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2021-02-19 13:03:48 +01:00 |
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Dolu1990
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e504afbf18
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fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
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2021-02-19 11:26:28 +01:00 |
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Dolu1990
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8537d18b16
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fpu improve fmax
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2021-02-17 16:35:52 +01:00 |
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Dolu1990
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1e647f799c
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fpu Fix VexRiscv integration and add software f64 tests (pass)
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2021-02-17 12:33:27 +01:00 |
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Dolu1990
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f180ba2fc9
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fpu double fixes
DataCache now support wide load/store
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2021-02-16 15:38:51 +01:00 |
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Dolu1990
|
7d3b35c32c
|
fpu f64/f32 pass all tests
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2021-02-12 14:48:44 +01:00 |
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Dolu1990
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9a25a12879
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fpu add FCVT_X_X
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2021-02-11 17:40:35 +01:00 |
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Dolu1990
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82dfd10dba
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fpu fix f32 tests for f64 fpu
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2021-02-11 16:42:17 +01:00 |
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Dolu1990
|
b6eda1ad7a
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fpu f64 load/store/mv/mul seems ok
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2021-02-11 16:07:47 +01:00 |
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Dolu1990
|
e97c2de837
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fpu f64 wip
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2021-02-10 19:27:26 +01:00 |
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Dolu1990
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88dffc21f7
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fpu f64 wip
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2021-02-10 13:20:17 +01:00 |
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Dolu1990
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889cc5fde2
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fpu refractoring
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2021-02-10 12:16:56 +01:00 |
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Dolu1990
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1fe993ad10
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fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully
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2021-02-09 18:35:47 +01:00 |
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Dolu1990
|
bf6a64b6b5
|
fpu sgnj / fclass / fmv pass
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2021-02-08 15:29:50 +01:00 |
|
Dolu1990
|
bf0829231d
|
fpu min max pass
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2021-02-06 14:08:21 +01:00 |
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Dolu1990
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008fadeaa9
|
fpu eq lt le pass testfloat
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2021-02-06 13:20:27 +01:00 |
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Dolu1990
|
6170243283
|
fpu got exception flag right for add/sub/mul/i2f/f2i
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2021-02-05 16:24:14 +01:00 |
|
Dolu1990
|
936e5823dc
|
fpu test wip
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2021-02-04 12:41:49 +01:00 |
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Dolu1990
|
3710fd3492
|
fix synthesis bench
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2021-02-04 12:41:31 +01:00 |
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Dolu1990
|
02b5b9b05c
|
fpu load subnormal and i2f now use single cycle shifter
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2021-02-03 16:48:09 +01:00 |
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Dolu1990
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8e7e736e3e
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Merge branch 'dev' into fpu
# Conflicts:
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/fpu/FpuCore.scala
# src/main/scala/vexriscv/ip/fpu/Interface.scala
# src/test/scala/vexriscv/ip/fpu/FpuTest.scala
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2021-02-03 16:06:17 +01:00 |
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Dolu1990
|
8eb8356dea
|
fpu wip
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2021-02-03 14:28:02 +01:00 |
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Dolu1990
|
1d0eecdcb0
|
fpu f2i rounding ok and full shifter
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2021-02-03 14:27:52 +01:00 |
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Dolu1990
|
ef011fa0d4
|
fpu moved 1 bit from round to mantissa
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2021-02-02 11:29:35 +01:00 |
|
Dolu1990
|
a87cb202b1
|
fpu i2f rounding ok
|
2021-02-01 16:12:38 +01:00 |
|
Dolu1990
|
d92adfbad0
|
SpinalHDL version++
|
2021-02-01 15:20:57 +01:00 |
|
Dolu1990
|
6ee45a1014
|
SpinalHDL version++
|
2021-02-01 12:28:33 +01:00 |
|
Dolu1990
|
98eaeaabc8
|
fix regression.mk typo
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2021-01-30 22:34:54 -01:00 |
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Dolu1990
|
6aa6191240
|
Merge branch 'master' into dev
# Conflicts:
# build.sbt
# src/main/scala/vexriscv/Riscv.scala
# src/main/scala/vexriscv/ip/DataCache.scala
# src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
# src/main/scala/vexriscv/plugin/MmuPlugin.scala
# src/test/cpp/regression/makefile
# src/test/scala/vexriscv/TestIndividualFeatures.scala
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2021-01-30 20:30:21 +01:00 |
|
Dolu1990
|
c51b0fcafe
|
fpu mul now pass all roundings
|
2021-01-29 22:30:19 +01:00 |
|
Dolu1990
|
0997592768
|
fpu mul sems all good excepted subnormal rounding
|
2021-01-29 16:13:49 +01:00 |
|
Dolu1990
|
3c4df1e963
|
fpu moved overflow rounding to writeback
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2021-01-29 14:37:52 +01:00 |
|
Dolu1990
|
fc3e6a6d0a
|
fpu add rounding is ok excepted infinity result
|
2021-01-28 20:26:43 +01:00 |
|
Dolu1990
|
1ae84ea83b
|
fpu added proper rounding for add (need to manage substraction)
|
2021-01-28 00:25:16 +01:00 |
|
Dolu1990
|
195e4c422d
|
fpu now integrate f2i shifter withing the subnormal shifter
|
2021-01-27 12:11:30 +01:00 |
|
Dolu1990
|
444bcdba0a
|
fpu merged i2f with load pipeline
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2021-01-26 15:28:09 +01:00 |
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Dolu1990
|
3334364f5f
|
fpu added more tests for min max sqrt div
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2021-01-26 12:50:23 +01:00 |
|
Dolu1990
|
f818fb3ba4
|
fpu got proper subnormal support, pass add/mul
|
2021-01-26 10:49:53 +01:00 |
|
Dolu1990
|
d6e8a5ef22
|
VexRiscvSmpLitex options refractoring
|
2021-01-23 20:16:58 +01:00 |
|
Dolu1990
|
ce143e06f2
|
VexRiscvSmpLitex --in-order-decoder --wishbone-memory added
|
2021-01-23 17:48:34 +01:00 |
|
Dolu1990
|
bdb5bc1180
|
fpu div implement some special values handeling
|
2021-01-22 20:47:31 +01:00 |
|
Dolu1990
|
7d79685fe2
|
fpu mul now support special floats values and better rounding
|
2021-01-22 18:15:45 +01:00 |
|
Dolu1990
|
4bd637cf88
|
fpu add now support special floats values and better rounding
|
2021-01-22 14:55:37 +01:00 |
|
Dolu1990
|
bcd140fc42
|
Add vexRiscvConfig.withMmu option
|
2021-01-21 13:28:09 +01:00 |
|
Dolu1990
|
ccd13b7e9e
|
fpu zero/nan wip
|
2021-01-21 12:13:25 +01:00 |
|
Dolu1990
|
50a69d8d4a
|
Merge pull request #163 from lindemer/pmp-warl
Make all PMP registers WARL according to specification
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2021-01-21 10:50:49 +01:00 |
Samuel Lindemer
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6c13e6458f
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Remove registers storing PMP region bounds
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2021-01-20 14:27:38 +01:00 |
|
Dolu1990
|
ac5844f393
|
fpu add signed i2f/f2i
|
2021-01-20 13:15:29 +01:00 |
|
Dolu1990
|
15d79ef330
|
fpu implement fclass and args for sub, fma, max, fcmp, fsgnj
|
2021-01-20 12:01:08 +01:00 |