Dolu1990
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2f8f4d5444
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SpinalHDL 1.1.5
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2018-03-13 15:45:56 +01:00 |
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Dolu1990
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7ea3e24183
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update readme perf
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2018-03-10 18:37:38 +01:00 |
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Dolu1990
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91031f8d75
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DivPlugin is now based MulDivIterativePlugin (Smaller)
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2018-03-10 13:31:35 +01:00 |
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Dolu1990
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f133e69fed
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fix readme toc
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2018-03-10 13:04:48 +01:00 |
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Dolu1990
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578e54376a
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Add MulDivIterativePlugin in readme
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2018-03-10 12:57:42 +01:00 |
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Dolu1990
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e437a1d44e
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Add division support in the MulDivInterativePlugin
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2018-03-09 22:41:47 +01:00 |
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Dolu1990
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36438bd306
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iterative mul improvments
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2018-03-09 20:00:50 +01:00 |
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Dolu1990
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674ab2c594
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experimental iterative mul/div combo
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2018-03-09 19:07:26 +01:00 |
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Dolu1990
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5228a53293
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MuraxSim improve simulation Speed
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2018-03-06 12:20:39 +01:00 |
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Dolu1990
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9b2cd7b234
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MuraxSim add switch
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2018-03-06 12:17:15 +01:00 |
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Dolu1990
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53970dd284
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SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
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2018-03-05 14:34:59 +01:00 |
Dolu1990
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b159ccf8ed
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Update README.md
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2018-02-27 22:43:53 +01:00 |
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Dolu1990
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ccad64def5
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Pipeline CSR isWrite
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2018-02-26 10:19:33 +01:00 |
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Dolu1990
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2b6185b063
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Decoding logic : Add primes duplication removal
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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2b6f43cef8
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Fix Murax memory mapping range
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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5260ad5c35
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Decoding lib cleaning
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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137b1ee32c
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Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
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2018-02-22 22:36:13 +01:00 |
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Dolu1990
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d957934949
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Fix ICache exception priority over miss reload
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2018-02-19 22:44:46 +01:00 |
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Dolu1990
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0270ee26fa
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Merge remote-tracking branch 'origin/reworkInstructionCache'
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2018-02-18 23:52:02 +01:00 |
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Dolu1990
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8ac4d72623
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Update readme
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2018-02-18 23:48:20 +01:00 |
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Dolu1990
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d0e963559a
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Update readme with the new ICache implementation
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2018-02-18 23:48:11 +01:00 |
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Dolu1990
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93110d3b95
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Add jump priority managment in PcPlugins
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2018-02-16 14:27:20 +01:00 |
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Dolu1990
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506e0e3f60
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New faster/smaller/multi way instruction cache design.
Single or dual stage
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2018-02-16 02:21:08 +01:00 |
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Dolu1990
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3853e0313b
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SynthesisBench cleaning/experiments
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2018-02-11 14:53:42 +01:00 |
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Dolu1990
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2a336c2812
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update readme
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2018-02-09 00:56:14 +01:00 |
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Dolu1990
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0e6ae682b1
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Add architecture section describing plugins in the readme
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2018-02-09 00:44:27 +01:00 |
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Dolu1990
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57ebfee2e6
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Add more axi bridges
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2018-02-08 21:39:22 +01:00 |
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Dolu1990
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fc5d89ad03
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Update README.md
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2018-02-08 01:07:51 +01:00 |
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Dolu1990
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967a0c4caf
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Update README.md
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2018-02-08 01:01:14 +01:00 |
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Dolu1990
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b1bd758fd2
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Update README.md
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2018-02-08 01:01:01 +01:00 |
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Dolu1990
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3ee111e100
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Update readme (gcc stuff)
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2018-02-05 16:34:10 +01:00 |
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Dolu1990
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d4b05ea365
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Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
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2018-02-05 16:16:27 +01:00 |
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Dolu1990
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4729e46763
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Add DummyFencePlugin
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2018-02-03 12:28:53 +01:00 |
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Dolu1990
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0bc3a1a314
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Update README.md
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2018-02-02 17:18:47 +01:00 |
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Dolu1990
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3d97c1f2f2
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Update README.md
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2018-02-02 14:47:07 +01:00 |
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Dolu1990
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f13dba847c
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Add custom csr gpio example
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2018-02-02 11:14:55 +01:00 |
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Dolu1990
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b7d8ed8a81
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Add onWrite/onRead/isWriting/isReading on the CsrPlugin
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2018-02-01 21:28:28 +01:00 |
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Dolu1990
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4ee2482cbf
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Fix custom_csr regression against random ibus stall
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2018-01-31 18:33:21 +01:00 |
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Dolu1990
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d2e5755df4
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revert removed code by mistake
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2018-01-31 18:29:30 +01:00 |
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Dolu1990
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30b05eaf96
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Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
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2018-01-31 18:13:42 +01:00 |
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Dolu1990
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42e677ec0d
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1.40 DMIPS/Mhz update
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2018-01-29 15:24:14 +01:00 |
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Dolu1990
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bdbf6ecf17
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BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
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2018-01-29 14:52:31 +01:00 |
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Dolu1990
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0d318ab6b9
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Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
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2018-01-29 13:17:11 +01:00 |
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Dolu1990
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307c0b6bfa
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Now mret and ebreak are only allowed in CSR machine mode
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2018-01-28 16:34:55 +01:00 |
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Dolu1990
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93da5d29bc
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Fix dhrystone referance log
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2018-01-28 16:34:55 +01:00 |
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Dolu1990
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3f9c8edc4c
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Update README.md
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2018-01-28 13:04:59 +01:00 |
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Dolu1990
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a98a0f72a6
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Update GCC information, update Murax performances
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2018-01-27 22:02:23 +01:00 |
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Dolu1990
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26732942e5
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Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
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2018-01-25 01:11:57 +01:00 |
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Dolu1990
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b3564e1b7e
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Fix Murax script flow (without rom file)
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2018-01-21 15:39:10 +01:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |