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VexRiscv
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1137 Commits

Author SHA1 Message Date
Dolu1990 0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990 594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990 8c25e73b9d Fix DIV negative values divided by zero 2018-10-11 22:18:21 +02:00
Dolu1990 c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990 8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990 40d85b8c70 Add fenceiGenAsAJump into BranchPlugin 2018-10-10 21:13:21 +02:00
Dolu1990 68f1ff3222 Add CsrPlugin ebreak support 2018-10-10 19:23:04 +02:00
Dolu1990 0662cc2797 Add GenMicro experiment to reduce ice40 area usage. 
IBusSimplePlugin now require cmdFork parameters to be set (no default)
 2018-10-03 22:08:57 +02:00
Dolu1990 48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1) 
IBusSimplePlugin now implement cmdForkPersistence option
 2018-10-03 16:24:10 +02:00
Dolu1990 c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990 0ada869b2d regression golden ref regfile is now sync with trl boot's random values 
wip
 2018-10-01 16:14:21 +02:00
Dolu1990 65a8d84d30 Introduce HAS_SIDE_EFFECT Stageable to solve sensitive instruction squeduling 
(uncached DBus TODO)
 2018-10-01 12:13:05 +02:00
Dolu1990 7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990 39c6bc11d6 Pass basic regression again 2018-09-29 19:04:20 +02:00
Dolu1990 5ad7c39f47 wip 2018-09-29 12:04:58 +02:00
Dolu1990 37a1970ad6 wip 2018-09-28 16:02:33 +02:00
Dolu1990 32cf90a162 Merge remote-tracking branch 'origin/dev' into Supervisor 2018-09-27 22:16:49 +02:00
Dolu1990 992c21ddd1 fix travis 2018-09-27 19:06:33 +02:00
Dolu1990 9a3510f63d Map all supervisor registers 2018-09-27 19:03:57 +02:00
Dolu1990 acd1ca422a wip 2018-09-27 18:24:40 +02:00
Dolu1990 a2d3cfbfc1 Remove unused file 2018-09-27 00:56:20 +02:00
Dolu1990 6dde73f97c Murax demo with XIP is now fully defined in SpinalHDL 2018-09-27 00:55:30 +02:00
Dolu1990 aff436ddcf Sync with SpinalHDL head 
Add mmu test into the dhrystone regression command
 2018-09-24 18:31:33 +02:00
Dolu1990 1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990 86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990 56fd73fbbc Add missing bin files 2018-09-23 19:26:11 +02:00
Dolu1990 bdc3246f5a Fix xip gitignore 2018-09-23 19:23:43 +02:00
Dolu1990 5024cc5616 Hardware breakpoint feature added 
Murax XIP debugging passed tests
 2018-09-20 13:11:20 +02:00
Dolu1990 ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990 b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990 3e17461cc7 Add optional XIP to Murax 2018-09-16 11:00:56 +02:00
Dolu1990 312e8b99b8 Merge remote-tracking branch 'origin/master' into dev 2018-09-16 10:21:31 +02:00
Dolu1990 fc1f4ec23a Merge remote-tracking branch 'origin/spinal_1.1.7' 2018-09-16 10:17:41 +02:00
Dolu1990 0476de8066 Move to SpinalHDL 1.2.0 2018-09-16 10:16:43 +02:00
Dolu1990 44bbfff4d4
Update README.md 
Add more information about the iBus behaviour
 2018-09-14 11:30:26 +02:00
Dolu1990 d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990 791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00
Dolu1990 0255f51cc5 Add unpipelined Wishbone support for uncached version 2018-08-24 16:41:34 +02:00
Snoopy87 304c8156a0
Update version 2018-08-24 06:51:10 +02:00
Dolu1990 39e1791067 Merge remote-tracking branch 'origin/dev' 2018-08-23 01:23:43 +02:00
Dolu1990 7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990 38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00
Dolu1990 dca1e5f438 revert RVC from murax 2018-08-17 23:12:45 +02:00
Dolu1990 f8c8643aa5 Merge remote-tracking branch 'origin/reworkFetcher' 2018-08-17 21:26:00 +02:00
Dolu1990 8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher 
Conflicts:
	README.md
	src/main/scala/vexriscv/TestsWorkspace.scala
	src/test/scala/vexriscv/Play.scala
 2018-08-17 20:56:51 +02:00
Dolu1990 9c7e089329 Fix ExternalInterruptArrayPlugin CSR ids 2018-08-17 20:38:33 +02:00
Dolu1990 819da2d0b4 remove freertos from travisautomated regressions tests 2018-08-17 20:07:09 +02:00
Dolu1990 1d3ac7830b restore tests without CSR catch all 2018-08-17 19:33:41 +02:00
Dolu1990 330ee14a23 final fetchRework commit ? 2018-08-17 19:13:23 +02:00
Dolu1990 91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue 2018-08-14 11:51:53 +02:00