Dolu1990
|
97c2dc270c
|
Fix typo
|
2020-06-04 10:11:30 +02:00 |
|
Dolu1990
|
89c13bedbd
|
Fix litex smp cluster sim
|
2020-06-03 16:31:54 +02:00 |
|
Dolu1990
|
73f88e47cb
|
Fix BmbToLitexDram coherency
|
2020-06-03 16:31:54 +02:00 |
|
Dolu1990
|
db50f04653
|
Add litexMpCluster
|
2020-06-03 16:31:54 +02:00 |
|
Dolu1990
|
08189ee907
|
DebugPlugin now support Bmb
|
2020-06-02 19:13:55 +02:00 |
|
Dolu1990
|
2942d0652a
|
fix Briey verilator
|
2020-06-01 11:18:25 +02:00 |
|
Dolu1990
|
5e5c730959
|
Add LitexSmpDevCluster with per cpu dedicated litedram ports
|
2020-05-29 10:56:55 +02:00 |
|
Dolu1990
|
bc4a2c3747
|
Fix SmpCluster jtag
|
2020-05-27 14:19:37 +02:00 |
|
Dolu1990
|
18cce053a3
|
Improve SingleInstructionLimiterPlugin to also include fetch stages
|
2020-05-27 14:19:17 +02:00 |
|
Dolu1990
|
a64fd9cf3b
|
Add CsrPlugin external hartid
d$ rsp/sync now decrement pendings by signal amount
|
2020-05-20 13:49:10 +02:00 |
|
Dolu1990
|
380afa3130
|
SpinalHDL 1.4.2
|
2020-05-20 13:45:52 +02:00 |
|
Dolu1990
|
c3540bc6e0
|
SpinalHDL 1.4.2
|
2020-05-20 10:37:52 +02:00 |
|
Dolu1990
|
24b676ce30
|
Merge pull request #124 from tomverbeure/uinstret
Add uinstret support.
|
2020-05-20 10:35:42 +02:00 |
Tom Verbeure
|
b901651ab5
|
Add default value of NONE to uinstret CSR.
|
2020-05-19 14:48:35 -07:00 |
|
Tom Verbeure
|
c74b03b4de
|
Add uinstret support.
|
2020-05-19 13:40:46 -07:00 |
|
Dolu1990
|
cf60989ae1
|
Litex smp cluster now blackboxify d$ data ram
|
2020-05-14 00:05:54 +02:00 |
|
Dolu1990
|
42fef8bbcd
|
Smp cluster now use i$ reduceBankWidth
|
2020-05-12 23:59:38 +02:00 |
|
Dolu1990
|
685c914227
|
Add i$ reduceBankWidth to take advantage of multi way by remaping the data location to reduce on chip ram data width
|
2020-05-12 23:59:38 +02:00 |
|
Dolu1990
|
0471c7ad76
|
Fix machineCsr test
|
2020-05-12 23:55:47 +02:00 |
|
Dolu1990
|
cb44a474fc
|
more smp cluster profiling
|
2020-05-12 13:25:55 +02:00 |
|
Dolu1990
|
63511b19a2
|
smp cluster add more profiling
|
2020-05-11 10:35:24 +02:00 |
|
Charles Papon
|
b592b0bff8
|
Add regression TRACE_SPORADIC, LINUX_SOC_SMP
regression golden model now properly sync dut exceptions
|
2020-05-09 17:00:13 +02:00 |
|
Dolu1990
|
0a159f06b2
|
update smp config
|
2020-05-07 22:50:36 +02:00 |
|
Dolu1990
|
0e76cf9ac8
|
i$ now support multi cycle MMU
|
2020-05-07 22:50:25 +02:00 |
|
Dolu1990
|
41ee8fd226
|
MmuPlugin now support multiple stages, D$ can now take advantage of that
|
2020-05-07 13:37:53 +02:00 |
|
Dolu1990
|
8e025aeeaa
|
more litex smp cluster pipelining
|
2020-05-07 13:18:11 +02:00 |
|
Dolu1990
|
fc0f3a2020
|
cleanup mmu interface
|
2020-05-06 18:05:20 +02:00 |
|
Dolu1990
|
6323caf265
|
MMU now allow $ to match tag against tlb pyhsical values directly
D$ retiming
D$ directTlbHit feature added for better timings
|
2020-05-06 17:09:46 +02:00 |
|
Dolu1990
|
ed4a89e4af
|
more pipelineing in Litex SMP cluster interconnect
|
2020-05-06 17:06:45 +02:00 |
|
Dolu1990
|
8043feebd5
|
More VexRiscv smp cluster probes
|
2020-05-06 17:06:17 +02:00 |
|
Dolu1990
|
09724e907b
|
play around with CSR synthesis impact on design size
|
2020-05-05 00:32:59 +02:00 |
|
Dolu1990
|
c16f2ed787
|
Add probes in SmpCluster sim
|
2020-05-04 12:54:28 +02:00 |
|
Dolu1990
|
b0f7f37ac8
|
D$ now support memDataWidth > 32
|
2020-05-04 12:54:16 +02:00 |
|
Dolu1990
|
93b386e16e
|
litex smp cluster now use OO decoder
|
2020-05-02 23:44:58 +02:00 |
|
Dolu1990
|
f0745eb0d9
|
update SMP line size to 64 bytes
|
2020-05-02 23:44:27 +02:00 |
|
Dolu1990
|
09ac23b78f
|
Fix SMP fence lock when 4 stages CPU
|
2020-05-01 12:45:16 +02:00 |
|
Dolu1990
|
f5f30615ba
|
Got litex SMP cluster to work on FPGA
|
2020-05-01 11:14:52 +02:00 |
|
Dolu1990
|
dc0da9662a
|
Update SMP fence (final)
|
2020-05-01 11:14:11 +02:00 |
|
Dolu1990
|
7c50fa6d55
|
SmpCluster now use i$ line of 64 bytes
|
2020-04-29 14:03:00 +02:00 |
|
Dolu1990
|
9e9d28bfa6
|
d$ now implement consistancy hazard by using writeback redo
|
2020-04-29 14:02:41 +02:00 |
|
Dolu1990
|
86e0cbc1f3
|
I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage
|
2020-04-29 13:59:43 +02:00 |
|
Dolu1990
|
7b80e1fc30
|
Set SMP workspace to use i$ memDataWidth of 128 bits
|
2020-04-28 22:11:41 +02:00 |
|
Dolu1990
|
eee9927baf
|
IBusCachedPlugin now support memory data width multiple of 32
|
2020-04-28 22:10:56 +02:00 |
|
Dolu1990
|
23b8c40cab
|
update travis verilator
|
2020-04-28 16:19:00 +02:00 |
|
Dolu1990
|
03a0445775
|
Fix SMP for configuration without writeback stage.
Include SMP core into the single core tests regressions
|
2020-04-28 15:50:20 +02:00 |
|
Dolu1990
|
4a49b23636
|
Fix regression
|
2020-04-28 14:38:27 +02:00 |
|
Dolu1990
|
3ba509931c
|
Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax
|
2020-04-27 17:38:06 +02:00 |
|
Dolu1990
|
5fd0b220cd
|
CsrPlugin add openSbi config
|
2020-04-27 17:37:30 +02:00 |
|
Dolu1990
|
0c59dd9ed3
|
SMP fence now ensure ordering for all kinds of memory transfers
|
2020-04-27 17:37:15 +02:00 |
|
Dolu1990
|
3fb123a64a
|
fix withStall
|
2020-04-21 21:20:54 +02:00 |