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f4pga-examples
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447 Commits

Author SHA1 Message Date
Alessandro Comodi d912762861
Merge pull request #159 from antmicro/update-eos-s3 
eos-s3: update environment, requirements and toolchain
 2021-07-02 14:35:27 +02:00
Alessandro Comodi 2dbe7e8b5a build-examples: fix conda-prep-env instructions 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-02 13:17:05 +02:00
Alessandro Comodi a5837bb0ba eos-s3: update environment, requirements and toolchain 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-07-02 12:51:20 +02:00
Joshua Fife b8a300db26 Changed some formatting, made naming consistent, and clarified info on SystemVerilog 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-30 09:21:21 -06:00
Joshua Fife 649a694960 Fixed merge conflict 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-26 18:43:21 -06:00
WhiteNinjaZ 2118438a25 Delete docFeedback.md 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-26 17:08:37 -06:00
Joshua Fife c3f494d7fc Made instructions clearer and added some information on the ifeq/else ifeq blocks 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-25 18:26:22 -06:00
Joshua Fife f3115cbe40 Changes rough draft 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-25 16:23:44 -06:00
Joshua Fife 2111fcc323 few makefile instruction changes 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-25 12:12:23 -06:00
Brent Nelson eb06e989ea Made two minor text edits. 
Signed-off-by: Brent Nelson <nelson@ee.byu.edu>
 2021-06-23 13:54:10 -06:00
Brent Nelson 49231bde93 Added list of comments on documentation. 
Signed-off-by: Brent Nelson <nelson@ee.byu.edu>
 2021-06-23 13:53:41 -06:00
Brent Nelson ddb9fe4b42 Added term symbiflow-examples in place of symbiflow in a couple of places 
Signed-off-by: Brent Nelson <nelson@ee.byu.edu>
 2021-06-23 13:51:42 -06:00
Brent Nelson a8590f707e Added links to new pages on main index page 
Signed-off-by: Brent Nelson <nelson@ee.byu.edu>
 2021-06-23 13:33:17 -06:00
Joshua Fife 46a7ce1fc7 Revised draft for Personal Designs 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-19 19:40:16 -06:00
Joshua Fife 5b80239847 Merge branch 'personal_designs' 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-18 12:21:09 -06:00
Alessandro Comodi c24275fa54
Merge pull request #157 from antmicro/fix-litex 
xc7: fix litex execution in CI
 2021-06-18 13:39:01 +02:00
Alessandro Comodi ba3ee5c49c xc7: fix litex execution in CI 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 10:36:36 +02:00
Alessandro Comodi 524f81a018
Merge pull request #111 from antmicro/litex-example 
Litex example
 2021-06-18 10:29:59 +02:00
Alessandro Comodi d39372ae87 litex_demo: update litex version 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 09:32:41 +02:00
Alessandro Comodi 22358ff170 litex: use default baud rate of 115200 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 09:32:41 +02:00
Alessandro Comodi a0b165eb90 xc7: added litex to readme 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 09:32:41 +02:00
Alessandro Comodi dc44e93754 xc7: linux_litex: remove litex example 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 09:32:41 +02:00
Alessandro Comodi 832bbfb67d env: add riscv64 unknown elf 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 09:32:04 +02:00
Filip Kokosinski 63d392b21c xc7: add picorv32 and vexriscv litex example 
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-06-18 09:31:25 +02:00
Joshua Fife c451dae1ac Added extra XDC PCF SDC info 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-15 17:16:03 -06:00
WhiteNinjaZ 05e32fe4bb Merge branch 'SymbiFlow:master' into master 2021-06-11 10:25:32 -06:00
Alessandro Comodi ca3f9ce817
Merge pull request #152 from carlosedp/bump-yosys-plugins 
Bump yosys plugins to leverage xc7 XDC dicts
 2021-06-11 13:39:46 +02:00
Carlos de Paula e596c0cf74 Bump yosys plugins to leverage xc7 XDC dicts 
Signed-off-by: Carlos de Paula <me@carlosedp.com>
 2021-06-10 12:38:54 -03:00
Joshua Fife b6932ed300 Rough Makefile Instructions 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-08 20:48:25 -06:00
Joshua Fife 1cafeeff8d Added instructions for Makefile 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-08 17:59:33 -06:00
Joshua Fife 52ba45644e Rough Draft 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-08 12:42:12 -06:00
Joshua Fife 85096f29cd A few minor clarifications on running examples (modified to include textual instructions) 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-02 17:19:59 -06:00
Joshua Fife fa8c64a13a A few minor clarifications on running examples (modified to include textual instructions) 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-01 16:20:57 -06:00
Joshua Fife 927379d5a3 A few minor clarifications on running examples 
Signed-off-by: Joshua Fife <jpfife17@gmail.com>
 2021-06-01 16:20:28 -06:00
Karol Gugala 043e59355f
Merge pull request #145 from cjearls/addingNexys4DDRtoPicoSoCSigned 
adding support for the Nexys4DDR to PicoSoC example
 2021-05-18 15:22:36 +02:00
Karol Gugala 453fa68a21
Merge pull request #147 from ryancj14/formatters 
Adding Python, JSON, and Verilog Formatters to symbiflow-examples
 2021-05-17 22:54:47 +02:00
Ryan Johnson 9b953d9f75 formatted files 
Signed-off-by: Ryan Johnson <ryancj14@gmail.com>
 2021-05-13 12:07:40 -06:00
Ryan Johnson 1baae70b14 current temporary fix for environments 
Signed-off-by: Ryan Johnson <ryancj14@gmail.com>
 2021-05-13 12:07:40 -06:00
Ryan Johnson 0da09dafff changes after initial review 
Signed-off-by: Ryan Johnson <ryancj14@gmail.com>
 2021-05-13 12:07:04 -06:00
Ryan Johnson a166626b25 Initial changes to implement formatters 
Signed-off-by: Ryan Johnson <ryancj14@gmail.com>
 2021-05-13 12:06:49 -06:00
Chandler Jearls ab4806984b Something must have been wired incorrectly before. Now, the USB-UART is working correctly without any issues 
Signed-off-by: Chandler Jearls <cjearls@vt.edu>
 2021-05-02 22:02:45 +00:00
Chandler Jearls 81b697fa0d adding support for the Nexys4DDR to PicoSoC example 
Signed-off-by: Chandler Jearls <cjearls@vt.edu>
 2021-04-30 14:46:24 +00:00
Karol Gugala ffebb33ee0
Merge pull request #142 from cjearls/addingNexys4DDRtoCounterTest 
added support for Nexys4DDR board in counter_test
 2021-04-27 10:03:38 +02:00
Chandler Jearls d2b0747fbe fixed a small typo in collect_readmes.py 
Signed-off-by: Chandler Jearls <cjearls@vt.edu>
 2021-04-21 17:52:09 +00:00
Chandler Jearls 8c67e280e1 added Nexys4DDR to the documentation 
Signed-off-by: Chandler Jearls <cjearls@vt.edu>
 2021-04-21 17:48:13 +00:00
Chandler Jearls 1e92d9c288 added support for Nexys4DDR board in counter_test 
Signed-off-by: Chandler Jearls <cjearls@vt.edu>
 2021-04-21 16:34:26 +00:00
TCal 9a114c44c0
Merge pull request #135 from antmicro/update-pckgs 
xc7: update packages
 2021-03-30 08:23:34 -07:00
Alessandro Comodi cdb36f5489 xc7: update packages 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-03-26 14:52:22 +01:00
Karol Gugala 0a4eb83b37
Merge pull request #134 from antmicro/fix-litex-demo 
xc7: litex: fix arty target
 2021-03-26 14:47:34 +01:00
Karol Gugala ea3fb3a86c xc7: litex: fix arty target 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-03-26 09:23:04 +01:00