4e974738d1
phy/lpddr5: fix column address encoding/decoding
2021-10-26 12:22:30 +02:00
914d018cf8
phy/sim_utils: support low wait times (0/1) in PulseTiming
2021-10-26 12:22:30 +02:00
2671508a11
phy/lpddr5: add simulation SoC
2021-10-26 12:22:30 +02:00
7cdf0e11ca
phy/lpddr5: add unit tests
2021-10-26 12:22:30 +02:00
136be83749
frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width.
2021-10-06 18:05:48 +02:00
3d3bf623aa
frontend/fifo: Simplify, fix corner cases.
2021-09-23 23:22:51 +02:00
dd24073633
test/test_fifo: Use 4 x DRAM data-width in Bypass mode to use Pre/Post-Converter.
2021-09-23 18:57:00 +02:00
2d4a47f260
frontend/fifo: Add initial optional/automatic Bypass implementation to LiteDRAMFIFO.
...
Bypass will provide lower latency and configurable data-width.
2021-09-21 19:23:36 +02:00
89af25a697
phy/utils: DFI rate converter for creating PHY wrappers at slower clocks
2021-08-04 12:30:56 +02:00
43036c9576
test: update *_init.h reference
2021-08-04 12:30:56 +02:00
2200bd43a5
test/reference: update headers to include SDRAM_PHY_DFI_DATABITS
2021-08-04 12:30:56 +02:00
91cae335e5
init: add parentheses around #define with an expression
2021-08-04 12:30:56 +02:00
a3aa4907f1
phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache.
...
(see #255 ).
2021-07-02 09:24:11 +02:00
317072a198
litedram_gen: Add initial SDRAM support (with ULX3S example).
2021-07-02 09:01:31 +02:00
34fbe01a78
test/phy_common: make chunk size in PadsHistory summary configurable
2021-06-22 11:41:44 +02:00
eb6e7a1514
test/lpddr4: move dfi_data_to_dq to common code
2021-06-22 11:41:44 +02:00
fcda73a175
test/phy_common: simplify calls to run_simulation
2021-06-22 11:41:44 +02:00
da769094fd
phy/lpddr4: fix edge case error with CommandsPipeline ignoring a command
...
Command was being ignored when it occurred on the last phase and
the next command would invalidate the first phase. Now it is fixed
and a regression test is included. A fix in ConstBitSlip has been added
due to wrong Verilog being generated with cycles=1, register=False.
2021-06-22 11:40:51 +02:00
baf9c07858
phy/utils: improve ConstBitSlip:
...
* optional register=False to decrease latency by 1 cycle
* require explicit `cycles` as it influences latency (min_cycles
still can be used)
* add unit tests
2021-06-21 14:43:49 +02:00
4a96be86c0
test/lpddr4: move run_simulation wrapper to phy_common.py
2021-06-21 14:43:49 +02:00
1543fa4ace
phy/lpddr4: extract common test helpers for use when testing other PHYs
2021-06-21 14:43:49 +02:00
47e8a59511
phy/lpddr4: extract SimulationPads and use it as a base class
2021-06-21 14:43:49 +02:00
8e563239f9
phy/lpddr4: extract common utilities
2021-06-21 13:22:15 +02:00
377d6fac6c
test/test_lpddr4: Disable failing test.
2021-06-08 15:07:53 +02:00
2fcc6fe552
test/test_ecc: Update.
2021-06-08 15:07:39 +02:00
dc6cb89737
also remove 'static' from cdelay() declarations in test suite
2021-05-26 12:09:26 -04:00
b8cd26fa52
test/refefence: Update.
2021-05-18 11:26:40 +02:00
0877a81b4b
test/test_init: Add simple way to update references.
2021-05-18 11:26:19 +02:00
63358ee666
test/reference: Update.
2021-04-28 18:21:27 +02:00
886f60d32c
test/reference: Update.
2021-04-23 11:26:30 +02:00
7028944acd
lpddr4: add missing copyright comments
2021-04-01 10:07:02 +02:00
e860d86f3f
lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default)
2021-03-25 15:31:58 +01:00
0ecb1340f5
lpddr4/test: fixes: use 2tCK write preamble, update read latency
2021-03-25 15:31:05 +01:00
5c6796b92a
lpddr4: change MRW command encoding to avoid changing BIOS code
2021-03-25 15:30:48 +01:00
eb1d900c24
lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE
2021-03-25 15:29:17 +01:00
4415a3eaf5
lpddr4: improve simulation and Verilator tests runner
2021-03-25 15:19:16 +01:00
2ab763ac5e
lpddr4: add double-rate PHY, clean up and improve PHY implementation
2021-03-25 15:19:16 +01:00
183f1643aa
lpddr4: add support for MASKED-WRITE
2021-03-25 15:19:16 +01:00
05ed238829
lpddr4: split implementation into multiple files in separate directory
2021-03-25 15:19:16 +01:00
ee9c2b4cf7
lpddr4: implement ZQC through MPC and include it in init sequence
...
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
2021-03-25 15:19:16 +01:00
6943a1a4a5
lpddr4: initial PHY logic and simulation tests
2021-03-25 15:19:08 +01:00
2d021c842e
test/reference: update.
2021-02-16 18:35:53 +01:00
2c60861929
Merge pull request #232 from antmicro/jboc/init-mr
...
init: make the write leveling MR bit configurable
2021-02-02 09:36:46 +01:00
b3ce582891
test: update ddr3 and ddr4 reference headers to new MR_WLVL defines
2021-01-29 12:49:19 +01:00
a1e7d805ec
test: improve error messages when comparing files in test_init.py
2021-01-28 17:44:13 +01:00
c29c898af4
platforms/targets: switch to LiteX-Boards.
2021-01-04 14:11:32 +01:00
103072c68a
test/reference: update.
2020-12-17 18:21:53 +01:00
b6252345af
test/reference: update ddr4.
2020-11-17 17:12:02 +01:00
df73b982ee
test/reference: update
2020-10-12 18:50:31 +02:00
39178ce460
test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
2020-10-02 12:30:19 +02:00
Jędrzej Boczar
Florent Kermarrec
Gabriel Somlo