6d09a47103
Merge pull request #73 from softerhardware/master
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Additional DDR3 and DDR4 SDRAMModules
2019-01-26 15:06:37 +01:00
92df55f234
travis: change tests order, comment test_examples for now (need to install the CPU toolchain to travis)
2019-01-26 15:00:16 +01:00
8e6ad4cc75
Additional DDR3 and DDR4 SDRAMModules
2019-01-25 17:54:14 -08:00
2d4b5ba775
core/crossbar: cosmetic
2019-01-22 13:56:35 +01:00
429d3a89de
test/common: set rdata_valid_rand_level default value to 0
2019-01-21 16:54:23 +01:00
9ddb3e2113
travis: set python version to 3.6
2019-01-21 16:36:17 +01:00
cc3880423a
Merge pull request #72 from EwoutH/master
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Add Travis CI
2019-01-21 16:35:32 +01:00
8e01cba7e6
Add Travis CI ( #1 )
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* Create .travis.yml
* Change Python version to 3.6
* Change OS to Linux 1604 and Python to version 3.7
* Set directory
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Update .travis.yml
* Split test in jobs
* Remove recursive
* Fix jobs
* Add litex --recursive
* Removed .py's in jobs
* re-added recursive
* Move tests to env:
* Python 3.5 test
* Run init and common tests always
2019-01-21 15:59:42 +01:00
031746a53c
frontend/bist: fix for data_width < 31 (16 bits SDRAMs)
2019-01-18 17:56:32 +01:00
b4c552a77f
core/multiplexer: fix command steering for nphases=1 (SDRAM), thanks jfng
2019-01-17 09:06:09 +01:00
224a423082
common: allow setting electrical settings with DDR4
2019-01-08 17:00:57 +01:00
fc3a192a87
phy/gensdrphy: make CAS latency configurable
2019-01-08 09:44:58 +01:00
b4ee95c3e3
sdram_init: generate ddrx_mr1 only if mr1 is not None
2019-01-07 22:59:20 +01:00
2483d25f79
test/test_ecc: update
2019-01-04 10:43:57 +01:00
6757a14d51
frontend/ecc: add error injection capability
2019-01-04 10:43:51 +01:00
7eee80da19
frontend/ecc: add description, rename dec signal to ded
2019-01-04 08:44:05 +01:00
14c6062b00
core/crossbar: remove "ROW_COL_BANK" address_mapping (need to be simulated)
2018-12-28 11:10:53 +01:00
180b3d2cc1
modules: adjust MT48LC16M16 timings
2018-12-27 22:25:59 +01:00
906edf1917
phy/gensdrphy: make cke/dm optional.
2018-12-23 23:10:04 +01:00
81fa19e58d
phy/usddrphy: fix DRC REQP-1665.
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When the ODELAYE3 ODELAYE3 DELAY_TYPE is FIXED, the RST pin should be GND.
2018-12-19 11:37:06 +01:00
c275755473
phy/usddrphy: add iodelay_clk_freq parameter
2018-12-19 10:43:17 +01:00
62a31de21f
phy: rename KUSDDRPHY to USDDRPHY since compatible with Kintex/Virtex Ultrascale
2018-12-18 11:31:41 +01:00
e91366cd31
frontend/axi: use buffered SyncFIFO on datapath (reduce resource usage)
2018-12-18 10:57:05 +01:00
da6fc8c39b
README: add Kintex Ultrascale PHY
2018-12-17 16:08:57 +01:00
8993e8b798
core/refresher: fix refresh regression
2018-12-17 15:31:27 +01:00
83f763f7b8
phy: replace wdly_dqs_taps with half_sys8x_taps (similar to what is implemented on 7-series)
2018-12-17 11:42:13 +01:00
28b7d3264c
phy/kusddrphy: use rdly_dq_bitslip_rst CSR for bitslip reset
2018-12-17 11:04:45 +01:00
1ece2ca7b7
phy/dfi: set act_n reset value to 1
2018-12-17 08:56:00 +01:00
057200665f
phy/kusddrphy: remove ResetSignal on ODELAYE3/ISERDESE3 that are dynamically adjusted, reduce sys latency
2018-12-13 18:52:54 +01:00
57ebcc53ca
sdram_init/ddr4: enable dll
2018-12-13 18:51:12 +01:00
7a2ff338f5
sdram_init/get_sdram_phy_py_header: generate mr1 value, fix init_sequence identation
2018-12-13 16:30:29 +01:00
33ff34b622
core/refresher: use self.sync to fix build (verilog wire vs reg...)
2018-12-07 17:46:43 +01:00
8419f2846d
core: split refresher, expose it and allow it to be reloaded externally.
2018-12-07 10:15:54 +01:00
8ec0bc678e
modules: improve the way we define DDR4 banks/groups
2018-12-06 21:16:37 +01:00
1618a7636a
phy: add KUSDDRPHY to __init__.py
2018-12-06 21:15:47 +01:00
d6350d9fec
test/test_axi: reduce rand_level on writes
2018-12-05 11:44:38 +01:00
282b60e94c
frontend/axi: simplify LiteDRAMAXI2NativeW logic
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Accept the Address/Data only if:
- Address & Data request are *both* valid.
- Data buffer is not full.
2018-12-05 11:44:23 +01:00
6778c72665
test/test_axi: cleanup, all tests passings.
2018-12-03 08:01:33 +01:00
ebb1d3c762
frontend/axi/LiteDRAMAXI2NativeW: be sure that we already have the data before sending the command to the controller
2018-12-01 12:11:22 +01:00
0d5e5543fb
frontend/axi: expose aw_burst2beat/ar_burst2beat
2018-11-30 12:32:15 +01:00
da65a804be
frontend/axi: expose w_buffer/r_buffer (can be useful for debug)
2018-11-30 11:59:22 +01:00
7f5d749c6b
test: add missing +x
2018-11-30 11:58:45 +01:00
7ef4869db9
test/test_axi: also add randomness on rdata.valid and wdata.ready
2018-11-30 11:22:04 +01:00
3db68cdd50
test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues)
2018-11-30 10:40:45 +01:00
190b1bd01f
test/test_axi/axi2native: add finer control on randomness
2018-11-30 09:40:13 +01:00
4f137b9334
test/test_axi/axi2native: add random on len, just use writes as reads
2018-11-29 23:45:38 +01:00
2a799e4f1d
test/test_axi: set size on axi2native test
2018-11-29 23:45:31 +01:00
e70d77e76e
phy/s7dddrphy: fix nphases = 2 (same code can be shared between nphases = 2 and nphases = 4)
2018-11-29 16:56:23 +01:00
170b3dc67d
frontend/wishbone: set aw/ar size on LiteDRAMWishbone2AXI
2018-11-26 10:37:28 +01:00
9a255062e0
frontend/wishbone: fix wishbone.err on LiteDRAMWishbone2AXI
2018-11-26 08:56:00 +01:00
enjoy-digital
Steve Haynal - VSD Engineering
Ewout ter Hoeven