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616 Commits

Author SHA1 Message Date
Florent Kermarrec fbd7ae3e62 modules: make IS43TR16128B consistent with others SDRAMModules 2019-05-28 10:02:02 +02:00
enjoy-digital 02448a3670
Merge pull request #83 from ambrop72/IS43TR16128B_125K 
modules/ddr3: add IS43TR16128B_125K
 2019-05-28 09:59:57 +02:00
Ambroz Bizjak d1089701d4 modules/ddr3: add IS43TR16128B_125K 
This is the chip that is actually on my Arty A7 100T (there is no mention of this chip in the Arty reference, which claims it is MT41K128M16JT-125).
 2019-05-27 19:36:38 +02:00
enjoy-digital da68e21bad
Merge pull request #82 from gsomlo/gls-expose-csr 
examples/litedram_gen: allow direct access to CSR (I/O) registers
 2019-05-17 21:27:45 +02:00
Gabriel L. Somlo 65451f426a examples/litedram_gen: allow direct access to CSR (I/O) registers 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
[florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]
 2019-05-16 15:05:30 -04:00
Florent Kermarrec 50e1d478db PhySettings: add databits to allow SoC to compute memory size more easily 2019-05-10 15:44:44 +02:00
Florent Kermarrec b93412bbdc examples: remove verilog simulation 
Simulation was here just to show how to do system level simulation adn required
external component to work (stadalone init).
 2019-05-10 13:05:48 +02:00
Florent Kermarrec a7e46bb25c example/litedram_gen: reserve_nmi_interrupt no longer exists 2019-05-10 12:43:23 +02:00
enjoy-digital 094fc2e736
Merge pull request #79 from gsomlo/gls-ulong-addr 
sdram_init: use "unsigned long" for address values
 2019-05-01 12:08:44 +02:00
Gabriel L. Somlo 54d3312cc6 sdram_init: use "unsigned long" for address values 2019-04-29 15:00:13 -04:00
Florent Kermarrec 3caaa2eb13 common/tXXDController: revert Yosys workarounds 
Now fixed with https://github.com/YosysHQ/yosys/pull/850
 2019-04-29 14:24:31 +02:00
Florent Kermarrec 44bbb93620 phy: add copyrights 2019-04-29 09:16:53 +02:00
Florent Kermarrec 6ddc2c83e4 README: update 2019-04-27 09:47:48 +02:00
Florent Kermarrec 9190a76741 travis: simplify and add RISC-V toolchain to run examples 2019-04-22 08:17:10 +02:00
Florent Kermarrec e824288924 frontend/axi: move AXIBurst2Beat to LiteX 
Will be useful for others purposes.
 2019-04-19 12:14:13 +02:00
Florent Kermarrec be269da3fe frontend/axi: use definitions from LiteX 
AXI definitions were not present in LiteX when AXI support was added to LiteDRAM.
 2019-04-19 11:58:05 +02:00
Florent Kermarrec e81b5a11b8 sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning 2019-04-12 18:22:00 +02:00
Florent Kermarrec c4161cfbfe examples: update sim 2019-03-15 20:16:42 +01:00
Florent Kermarrec 201a0e2fb4 test/test_examples: add nexys4ddr 2019-03-15 20:10:50 +01:00
Florent Kermarrec 69afaf5a19 common: add separators, reorganize a bit 2019-03-15 20:08:08 +01:00
Florent Kermarrec 0bc241c2bf phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit 2019-03-14 23:50:36 +01:00
Florent Kermarrec c65ff974b6 phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers 2019-03-05 12:25:31 +01:00
Florent Kermarrec 4274db809e common/TXXDcontroller: fix for compatibility with Yosys and vendor tools 2019-03-04 12:48:42 +01:00
Florent Kermarrec a74d5c9d9e common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value 
Fix SDRAM build with Yosys
 2019-03-04 09:22:03 +01:00
enjoy-digital cec35f3efd
Merge pull request #77 from daveshah1/ecp5_75MHz 
ecp5ddrphy: Shift read position forwards to fix higher frequencies
 2019-03-02 22:34:12 +01:00
David Shah fa26dcdcb0 ecp5ddrphy: Shift read position forwards to fix higher frequencies 2019-03-02 19:14:14 +00:00
enjoy-digital 6715c1bd45
Merge pull request #76 from daveshah1/trellis_io 
ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs
 2019-02-25 19:26:45 +01:00
David Shah 691d9308b2 ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs 2019-02-25 18:03:05 +00:00
Florent Kermarrec 9057f510d2 phy: add ECP5 imports 2019-02-25 15:30:04 +01:00
Florent Kermarrec f660618295 phy: add initial ECP5DDRPHY 2019-02-25 14:44:01 +01:00
Florent Kermarrec 640194a5c9 examples: add nexys4ddr_config 2019-02-21 23:32:45 +01:00
Florent Kermarrec 0ac1af367a examples/litedram_gen: add DDR2 support 2019-02-21 23:32:23 +01:00
Florent Kermarrec f4184ec37a example/litedram_gen: update, add descriptions of config parameters 2019-02-21 23:19:52 +01:00
Florent Kermarrec 79806aad20 modules/ddr3: add MT41K64M16 2019-02-20 22:47:55 +01:00
Florent Kermarrec ea6b841dfe phy/s7ddrphy and usddrphy: add cmd_latency parameter 
On some boards, we need to delay command to have a optimal write_leveling window,
cmd_latency can be use to delay write data so that cwl is ensured.
 2019-02-19 18:00:23 +01:00
Florent Kermarrec fd3e9afbcd phy/s7ddrphy: fix cmd delays 2019-02-14 09:42:33 +01:00
Florent Kermarrec f61c8d93af phy/s7ddrphy: make clk/cmd odelaye2s configurable 
Required on some DDR3 boards of optimal write-leveling calibration
 2019-02-13 18:23:12 +01:00
Florent Kermarrec e0224f458c phy/usddrphy: make clk/cmd odelaye3s configurable 
Required on some DDR4 boards of optimal write-leveling calibration
 2019-02-13 12:06:17 +01:00
Florent Kermarrec d89b17177a modules/mt40a1g8: use _L (long) timings 2019-02-12 11:26:48 +01:00
Florent Kermarrec 2d4fdd1de4 litedram/sdram_init/ddr4: disable data mask (not required) 2019-02-12 10:52:39 +01:00
enjoy-digital 0b49cbbc84
Merge pull request #74 from softerhardware/master 
Update to MT40A1G8 that Phillip was successful with
 2019-02-09 07:10:15 +01:00
Steve Haynal - VSD Engineering d65377fa1f Update to MT40A1G8 that Phillip was successful with 2019-02-08 15:52:51 -08:00
Florent Kermarrec f2074542a1 sdram_init/ddr4: set data mask enable bit 2019-02-02 23:14:30 +01:00
enjoy-digital 6d09a47103
Merge pull request #73 from softerhardware/master 
Additional DDR3 and DDR4 SDRAMModules
 2019-01-26 15:06:37 +01:00
Florent Kermarrec 92df55f234 travis: change tests order, comment test_examples for now (need to install the CPU toolchain to travis) 2019-01-26 15:00:16 +01:00
Steve Haynal - VSD Engineering 8e6ad4cc75 Additional DDR3 and DDR4 SDRAMModules 2019-01-25 17:54:14 -08:00
Florent Kermarrec 2d4b5ba775 core/crossbar: cosmetic 2019-01-22 13:56:35 +01:00
Florent Kermarrec 429d3a89de test/common: set rdata_valid_rand_level default value to 0 2019-01-21 16:54:23 +01:00
Florent Kermarrec 9ddb3e2113 travis: set python version to 3.6 2019-01-21 16:36:17 +01:00
enjoy-digital cc3880423a
Merge pull request #72 from EwoutH/master 
Add Travis CI
 2019-01-21 16:35:32 +01:00