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949 Commits 5 Branches 14 Tags 5.7 MiB
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949 Commits

Author SHA1 Message Date
Florent Kermarrec ae5dc9f27a sdram_init: add initial DDR4 initialization 2018-11-05 09:32:08 +01:00
Florent Kermarrec 8181fea0da modules: add EDY4016A DDR4 2018-11-04 18:50:50 +01:00
Florent Kermarrec 346e64c3f2 frontend/ecc: fix typo 2018-11-04 17:07:00 +01:00
Florent Kermarrec 82c08c78c9 phy/gensdrphy: use tristate input 2018-10-29 19:27:26 +01:00
Florent Kermarrec 9ce84d96ec modules: add MT48LC16M16 (ulx3s) 2018-10-29 19:26:42 +01:00
Florent Kermarrec f36bcff49f phy/gensdrphy: cleanup/simplify pass 2018-10-19 18:26:45 +02:00
Florent Kermarrec da06715596 core/bankmachine: typo 2018-10-19 18:20:12 +02:00
Florent Kermarrec ab0d519ebb core: change cba_shift parameter to more explicit address_mapping parameter 2018-10-19 17:38:04 +02:00
Florent Kermarrec 230ea24113 core: simplify/cleanup pass 2018-10-19 17:21:06 +02:00
Florent Kermarrec 94b844d5b0 core/frontend: move crossbar to core 2018-10-19 15:07:39 +02:00
Florent Kermarrec 8d24163a86 phy/s7ddrphy: use our own bitslip module in fabric 
we could probably reduce added latency to 2 or 1 in the future.
 2018-10-18 13:40:58 +02:00
Florent Kermarrec 20d767532d phy/s7ddrphy: add additional_read_latency parameter 2018-10-15 11:10:16 +02:00
Florent Kermarrec f11506accd examples/litedram_gen: cleanup pins definition 2018-10-15 09:38:34 +02:00
Florent Kermarrec 75b314c8eb modules: update K4B2G1646F and use timings from datasheet 2018-10-15 08:51:08 +02:00
Florent Kermarrec b71ed354ad core/bankmachine: manage tRC 2018-10-15 08:34:41 +02:00
Florent Kermarrec 0abb3e4f5d modules: use tRAS and tRP to compute tRC (tRC = tRAS + tRP) 2018-10-15 08:34:18 +02:00
Florent Kermarrec 9a950f051a ecc: update core/test 2018-10-12 17:13:53 +02:00
Florent Kermarrec 8a0d0f09f9 phy/s7ddrphy: remove hacky bl8 variant (see #60) 2018-10-12 08:59:33 +02:00
Florent Kermarrec 5fe4868491 modules: add trrd to all ddr3 modules 2018-10-12 08:19:38 +02:00
enjoy-digital dbfa929bec
Merge pull request #59 from enjoy-digital/tRRD_Fix 
tRRD incorrectly specified
 2018-10-12 07:21:22 +02:00
john@csquare.ca 5315d279d3 tRRD incorrectly specified 2018-10-11 17:08:31 -04:00
Florent Kermarrec 167c0c91f6 remove partial reordering code in master, keep things in bank_reordering branch. 
we'll try to stabilize master without reordering, then do some refactoring/adding a test suite to ease adding proper reordering later
 2018-10-11 19:40:31 +02:00
Florent Kermarrec 828129ef40 core/bank_machine: simplify trascon 2018-10-10 17:48:11 +02:00
Florent Kermarrec 4fa64c8e96 core/bankmachine: remove trccon (activate_allowed not used) 2018-10-10 17:44:40 +02:00
John Sully feac98f399 core/bankmachine: use tXXDController everywhere (better timings) 2018-10-10 17:42:57 +02:00
John Sully bce411ec95 common: move tXXDController to common 2018-10-10 17:28:32 +02:00
Florent Kermarrec fef4701a45 core/multiplexer: select all ranks on refresh 2018-10-10 09:13:20 +02:00
Florent Kermarrec 3481d45c9b core/multiplexer: fix rank_decoder width 2018-10-09 14:24:39 +02:00
Florent Kermarrec 3b5a1ff906 modules: add K4B1G0446F 2018-10-08 17:36:32 +02:00
Florent Kermarrec 48c17ce8a4 modules: fix tWTR regression on MT46H32M32 2018-10-02 18:53:13 +02:00
Florent Kermarrec ad0a1d4215 modules: improve timings definition (keep retro-compatibility with previous definitions) 2018-10-02 10:32:45 +02:00
Florent Kermarrec 5b02791580 modules: add tCCD to all modules 2018-10-02 08:41:48 +02:00
Tim 'mithro' Ansell 6c7a804986 Adding tCCD for DDR2 modules. 2018-10-01 19:01:12 -07:00
208f5562d1 Merge branch 'master' of https://github.com/enjoy-digital/litedram 2018-10-01 19:36:05 -04:00
69eaf844e8 Fix DDR2 and below compilation failure 2018-10-01 19:35:20 -04:00
Florent Kermarrec 41a8a246b6 modules: express tFAW in ns 2018-10-01 19:41:30 +02:00
Florent Kermarrec 70620689a0 modules: split DDR3 in 2 categories: Chips and SO-DIMMs 2018-10-01 12:17:50 +02:00
Florent Kermarrec 0f46dc4ab7 modules: add DDR3-800 timings for MT41J128M16 and use it on arty example 2018-10-01 11:59:54 +02:00
Florent Kermarrec 426ae23d2a examples/litedram_gen: add sdram_module_speedgrade parameter 2018-10-01 11:48:15 +02:00
Florent Kermarrec 1bc016cf6c test: add test_examples 2018-10-01 11:29:08 +02:00
Florent Kermarrec f7f8169883 test: update downconverter/upconverter 2018-10-01 11:18:54 +02:00
Florent Kermarrec 8de1d91eac core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) 2018-10-01 11:18:39 +02:00
70516c40bf Merge branch 'master' of https://github.com/enjoy-digital/litedram 2018-09-30 22:17:45 -04:00
Florent Kermarrec 58209708e7 frontend/crossbar: fix #49 2018-09-29 20:09:07 +02:00
71f78d953e Fix reordering controller rejecting all commands 2018-09-29 13:52:20 -04:00
8f14211f00 Account for CWL in write to read timing 2018-09-29 12:39:40 -04:00
Florent Kermarrec 5fb8afe7e5 frontend/axi: omit bank in rdata connect 2018-09-28 23:44:12 +02:00
enjoy-digital 06ca53d2b2
Merge pull request #48 from enjoy-digital/staging 
Staging
 2018-09-28 23:29:41 +02:00
enjoy-digital 5a4d063f64
Merge branch 'master' into staging 2018-09-28 23:29:24 +02:00
Florent Kermarrec 5984eaa6da core: change api for out-of-order. (with_reordering passed to controller and not ports). 
We are not going to mix in-order/out-of-order ports
 2018-09-28 23:16:54 +02:00