When using the SDRAM PHY model without specified init data, the
generator still generates a bunch of $readmemh for each bank
reading mem.init, mem_1.init etc... all of which are 0-sized files.
This is cumbersome especially when using a standalone model in
an external project.
This is fixed by having the default bank_init be set to a list
of "None" rather than a list of empty lists.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
If the --sim argument is passed, this generates a model using
the simulation platform and simulated PHY.
Note: The data_width is set to 16 for now, which matches the
Arty. I haven't yet figured out how to extract that info from
the data we have in the .yml
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Name it wb_ctrl rather than just wb, which makes the resulting
core signal names a bit more descriptive. IE. The DRAM control
bus (by opposition to the use/data buss(es).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
On some standalone core implementations, such with Microwatt,
the main system bus is 64-bit, but the wishbone to access the
CSRs is 32-bit.
To avoid extra logic & muxes and just wire these together, it's
useful to be able to specify a larger alignemnt (64-bit) for the
CSRs so that the generated csr.h contains the right offsets.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Microwatt will want that as it uses init_done to select whether
to run the SDRAM init code or the user code at reset.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
For example on KC705, to only use the 4 first modules (bytes):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[0, 1, 2, 3])
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(ddram_pads,
[...]
On Arty, to only use the second module (byte):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[1])
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(ddram_pads,
[...]
Florent Kermarrec
Jędrzej Boczar
Benjamin Herrenschmidt
David Shah