Florent Kermarrec
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30c32f557c
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example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)
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2018-09-25 10:40:24 +02:00 |
Florent Kermarrec
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2a3cacb967
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core/bankmachine: minor cleanup on trc/tras
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2018-09-23 21:19:17 +02:00 |
enjoy-digital
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42ccf05e15
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Merge pull request #45 from enjoy-digital/tRAS_FIX
Implement tRAS
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2018-09-23 22:19:58 +02:00 |
John Sully
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79b1421878
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Auto precharge is too pessimistic, it will wait on its own for a valid time to execute
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2018-09-23 20:55:24 +02:00 |
John Sully
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177d7393f9
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Implement tRAS
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2018-09-23 19:42:46 +02:00 |
enjoy-digital
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59020270af
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Merge pull request #44 from enjoy-digital/tRC_Fix
This adds support for tRC timing parameters
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2018-09-23 18:09:15 +02:00 |
John Sully
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5f6b85703d
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This adds support for tRC timing parameters
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2018-09-23 17:56:07 +02:00 |
enjoy-digital
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1777720a0c
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Merge pull request #42 from enjoy-digital/HalfRateSequentialFix
We wait an extra cycle for no reason
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2018-09-23 15:04:42 +02:00 |
John Sully
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06c8c2afcf
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The actual fix
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2018-09-23 11:32:49 +02:00 |
John Sully
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e22580f9bd
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remove unnecessary file
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2018-09-23 11:22:25 +02:00 |
John Sully
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c028786702
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Fix overflow bug from code review
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2018-09-23 11:01:58 +02:00 |
enjoy-digital
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04aa04d123
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Merge pull request #43 from enjoy-digital/EfficencyFixes
Bank valid/ready refactor
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2018-09-23 09:40:14 +02:00 |
John Sully
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8447d69326
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We wait an extra cycle for no reason
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2018-09-23 01:29:19 +02:00 |
John Sully
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c4bd842cdf
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Fix many bugs
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2018-09-23 01:21:18 +02:00 |
John Sully
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fa0f3b2777
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Use the ready signal for cas_allowed so that arbitrators know not to iterate
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2018-09-22 17:15:19 +02:00 |
Florent Kermarrec
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c12404e00c
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README: Add ECC
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2018-09-19 11:42:13 +02:00 |
Florent Kermarrec
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3f4c14b068
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frontend/ecc: expose incident bits, change clear register name
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2018-09-19 11:33:49 +02:00 |
Florent Kermarrec
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b9aadf11d1
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frontend/axi: remove write buffer reservation (not needed)
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2018-09-19 10:53:40 +02:00 |
Tim 'mithro' Ansell
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ea1ac4d6d7
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s6ddrphy: Pass missing nranks parameter.
Fixes #41.
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2018-09-18 16:58:07 -07:00 |
Florent Kermarrec
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e5696ad3ef
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frontend/ecc: add enable csr
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2018-09-18 19:30:08 +02:00 |
Florent Kermarrec
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e6ef89a4d3
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frontend/axi: optimize burst2beat timings
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2018-09-18 19:15:40 +02:00 |
Florent Kermarrec
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6941285d3f
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frontend/ecc: split Write/Read path and add buffer to improve timings
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2018-09-18 17:23:18 +02:00 |
Florent Kermarrec
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041817df7a
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frontend/ecc: use csr instead of signal for control
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2018-09-18 16:23:54 +02:00 |
Florent Kermarrec
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b145b0c338
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frontend/axi: fix write response implementation
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2018-09-18 15:24:41 +02:00 |
Florent Kermarrec
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d23dbf6e57
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phy: add nranks to all phys
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2018-09-17 09:07:09 +02:00 |
Florent Kermarrec
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461b076624
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frontend/ecc: add ecc adapter
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2018-09-16 01:01:45 +02:00 |
Florent Kermarrec
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c84b58735a
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frontend: add initial ecc code (still need to be integrated)
Works but all combinatorial, will maybe need to be pipelined
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2018-09-15 23:37:59 +02:00 |
Florent Kermarrec
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a8d26724dd
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phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation
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2018-09-15 02:22:12 +02:00 |
Florent Kermarrec
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5719d71ace
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phy/s7ddrphy_halfrate_bl8: fix cs_n
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2018-09-15 00:47:33 +02:00 |
Florent Kermarrec
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36fa324291
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core/multiplexer: fix regression (introduced by multirank support)
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2018-09-12 07:14:59 +02:00 |
Florent Kermarrec
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42d0e5bbaa
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core/multiplexer: add more information on odt fixme
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2018-09-10 16:34:18 +02:00 |
Florent Kermarrec
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919b756261
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phy/model: pass nranks to Interface
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2018-09-10 15:17:07 +02:00 |
Florent Kermarrec
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f5c7b61704
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multirank: set default nranks to 1 if not specified
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2018-09-10 15:16:46 +02:00 |
Florent Kermarrec
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f3d403f1e0
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s7ddrphy: fix typo (reset_n --> cs_n)
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2018-09-10 04:44:35 +02:00 |
Florent Kermarrec
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37f1decfb2
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multirank: one cs_n/cke/odt/clk per rank
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2018-09-09 14:32:15 +02:00 |
Florent Kermarrec
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3e17d18b0c
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phy: add halfrate_bl8 variant for s7ddrphy
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2018-09-09 03:30:18 +02:00 |
enjoy-digital
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412e9a5c51
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Merge pull request #38 from enjoy-digital/multirank
Multirank
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2018-09-09 02:03:20 +02:00 |
Florent Kermarrec
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8ddc6c735d
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drive odt of all ranks, fixes and test non regression with 1 rank
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2018-09-09 01:52:24 +02:00 |
enjoy-digital
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d9c243037a
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Merge pull request #36 from JohnSully/timing_1
Fix failing timing
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2018-09-08 13:17:26 +02:00 |
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efd7a47890
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Fix failing timing
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2018-09-07 22:12:24 -04:00 |
Florent Kermarrec
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d4f434da3d
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dfii: send command to all ranks
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2018-09-07 18:40:46 +02:00 |
Florent Kermarrec
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b1c2739305
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initial multirank support (nbankmachines = nranks * (2**bankbits))
To see:
Configure the 2 ranks. (init commands, leveling)
How to drive ODT?
Pipeline stall while switching ranks?
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2018-09-07 18:34:08 +02:00 |
Florent Kermarrec
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cc481be81f
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examples: add sdram_rank_nb and user_ports_id_width
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2018-09-07 17:55:46 +02:00 |
Florent Kermarrec
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849b1f6c35
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frontend/axi: generate rlast signal
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2018-09-06 11:11:17 +02:00 |
Florent Kermarrec
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1fa73e4718
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test: update
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2018-09-06 11:10:45 +02:00 |
Florent Kermarrec
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7b61b68f68
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sdram_init: min value for wr is 5
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2018-09-05 23:40:04 +02:00 |
Florent Kermarrec
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1652ab95c8
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examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
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2018-09-05 09:13:47 +02:00 |
Florent Kermarrec
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1e64b7f492
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examples/litedram_gen: expose resp signals to user
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2018-09-05 08:51:27 +02:00 |
Florent Kermarrec
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700f76c599
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frontend/axi: add resp signals
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2018-09-05 08:50:28 +02:00 |
Florent Kermarrec
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47fed1b254
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frontend/axi: add last limitation
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2018-09-05 08:33:49 +02:00 |