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322 Commits 5 Branches 14 Tags 5.7 MiB
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322 Commits

Author SHA1 Message Date
ed4be0b2a0 Add write bank to out of order interface 2018-08-10 00:20:13 -04:00
Florent Kermarrec c28a754867 test: update 2018-08-09 10:54:42 +02:00
Florent Kermarrec f7f8452857 core: make rdata_bank optional (break cdc when enabled), fix some usecases 2018-08-09 10:54:30 +02:00
Florent Kermarrec 873b970fca frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup 2018-08-09 09:33:24 +02:00
enjoy-digital 26f3f016e1
Merge pull request #21 from JohnSully/outoforder 
Outoforder
 2018-08-09 09:20:55 +02:00
enjoy-digital 74c3c092ea
Merge pull request #20 from bunnie/400mhz-pr 
add 400MHz tap setting (valid for -3 and -2/2E speed grades)
 2018-08-09 08:20:29 +02:00
Tim Ansell 48230583b9
Adding comment to iodelay_tap_average dictionary. 2018-08-08 13:31:11 -07:00
bunnie d986b60e03 add 400MHz tap setting (valid for -3 and -2/2E speed grades) 2018-08-09 03:28:48 +08:00
Florent Kermarrec e02a251cde core: make tRRD definition optional and some cosmetic changes 2018-08-08 12:24:07 +02:00
bfa1d6aa7e remove debug prints 2018-08-03 15:24:08 -04:00
2fa2a6d9f2 Initial implementation of out of order controller 2018-08-03 15:21:17 -04:00
enjoy-digital 5d74eb249f
Merge pull request #19 from JohnSully/timing 
Fix timing issues (tRRD, tCCD, and tFAW)
 2018-07-31 21:37:28 +02:00
f1fea6dbd6 Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently 2018-07-31 13:31:49 -04:00
eb3f4a05f6 fix CAS to CAS timings (needs to account for multiple banks) 2018-07-31 01:57:55 -04:00
f0f5e6036b Add tRRD timing checks, and fix tFAW so it considers all banks 2018-07-30 23:45:52 -04:00
Florent Kermarrec f0f067fe7d phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical 2018-07-27 08:34:06 +02:00
Florent Kermarrec f560b9c182 core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating 2018-07-19 16:04:14 +02:00
Florent Kermarrec 2736ebccda setup.py: fix exclude, add example_designs to exclude 2018-07-19 11:22:53 +02:00
Florent Kermarrec e830526832 setup.py: exclude sim, test, doc directories 2018-07-18 09:39:33 +02:00
Florent Kermarrec 6d96bcc1e7 core/bankmachine: fix cas_count size when tccd == 1 2018-07-17 17:41:10 +02:00
Florent Kermarrec f4ad65e3c4 core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) 2018-07-16 18:39:59 +02:00
Florent Kermarrec eee89d4035 phy/s7ddrphy: add ddr2 support 2018-07-16 09:19:56 +02:00
Florent Kermarrec c9f2e30dcc core/controller: add simulation workaround for 1:2 ddr3 phy 2018-07-13 17:32:24 +02:00
Florent Kermarrec bd09471a03 phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) 2018-07-13 17:31:39 +02:00
Florent Kermarrec dec5378422 core/bankmachine: add CAS to CAS support (tCCD) 2018-07-13 15:03:04 +02:00
Florent Kermarrec 5bc35759f6 modules: add retro-compat on MT41J256M16 2018-07-12 10:54:50 +02:00
Florent Kermarrec c4dad2402c modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) 2018-07-10 12:13:59 +02:00
Florent Kermarrec 370b05ecf1 core/bankmachine: add Four Activate Window support (tFAW) 2018-07-09 17:27:58 +02:00
Florent Kermarrec d0ff536e0d phy/s7ddrphy: add specific bitslip reset 2018-07-06 19:27:18 +02:00
Florent Kermarrec 8ba7fcab23 core/bankmachine: simplify row change detection for auto precharge 2018-07-06 15:25:21 +02:00
Florent Kermarrec 3255a33b9e core/bankmachine: remove specific case for small cmd_buffer_depth 2018-07-06 14:49:12 +02:00
enjoy-digital d150e3b1ca
Merge pull request #12 from JohnSully/master 
Add auto-precharge support
 2018-07-06 14:41:08 +02:00
Florent Kermarrec 82b7199770 modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) 2018-07-06 14:32:13 +02:00
Florent Kermarrec f4b92b6142 phy/s7ddrphy: add nphases parameter to get functions 2018-07-04 21:55:43 +02:00
Florent Kermarrec d7d5d4a06f phy/s7ddrphy: add iodelay_clk_freq parameter 2018-07-02 13:43:15 +02:00
Florent Kermarrec f47ddb38e4 phy/s7ddrphy: add get_cl_cw function 2018-07-02 11:08:26 +02:00
Florent Kermarrec d9da7c54ee phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. 2018-06-28 18:50:56 +02:00
Florent Kermarrec ba16ebfb22 phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. 2018-06-12 15:36:39 +02:00
Florent Kermarrec 2bd7707e67 modules: add MT18KSF1G72HZ_1G6 2018-06-12 09:54:38 +02:00
6b0d5ceeae Prevent spurious precharge all commands caused by leaving A10 asserted during precharge 2018-05-03 14:29:39 -04:00
d0fcfb172f Auto-precharge now only fires when it needs to 2018-05-03 03:34:21 -04:00
Florent Kermarrec c23814961d phy/kusddrphy: follow more Xilinx recommandations 2018-03-13 22:33:33 +01:00
Florent Kermarrec 45da365b7f phy/kusddrphy: add odelaye3 on all outputs (to have identical delays on all outputs before software dq/dqs delay configuration) 2018-03-09 20:46:19 +01:00
Florent Kermarrec f905fda8ff phy/kusddrphy: use IOBUFDSE3 on dqs to be able to apply ODT=RTT_40 constraint 2018-03-09 13:01:48 +01:00
Florent Kermarrec e6a99d9cbc phy/kusddrphy: revert dqs preamble/postamble since not working for continous transfer, will need a proper implementation 2018-03-08 13:15:28 +01:00
Florent Kermarrec 66d99a3e36 phy/kusddrphy: add dqs preamble/postamble instead of always toggling on oe_dqs 2018-03-08 10:44:48 +01:00
Florent Kermarrec da4651ff19 phy/kusddrphy: add comment 2018-03-08 08:33:31 +01:00
Florent Kermarrec 0d7a7a99e0 phy/kusddrphy: store dqs taps init value in csr at startup 2018-03-07 23:32:39 +01:00
Florent Kermarrec b885f582f3 phy/kusddrphy: operate delays in time mode (to be able to specify 500ps delay on dqs) and add workaround to allow software to get number of taps for 500ps at init. 2018-03-07 16:23:27 +01:00
Florent Kermarrec 459060ede3 phy/kusddrphy: add en_vtc control 2018-03-07 12:14:16 +01:00