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691 Commits

Author SHA1 Message Date
enjoy-digital 59020270af
Merge pull request #44 from enjoy-digital/tRC_Fix 
This adds support for tRC timing parameters
 2018-09-23 18:09:15 +02:00
John Sully 5f6b85703d This adds support for tRC timing parameters 2018-09-23 17:56:07 +02:00
enjoy-digital 1777720a0c
Merge pull request #42 from enjoy-digital/HalfRateSequentialFix 
We wait an extra cycle for no reason
 2018-09-23 15:04:42 +02:00
John Sully 06c8c2afcf The actual fix 2018-09-23 11:32:49 +02:00
John Sully e22580f9bd remove unnecessary file 2018-09-23 11:22:25 +02:00
John Sully c028786702 Fix overflow bug from code review 2018-09-23 11:01:58 +02:00
enjoy-digital 04aa04d123
Merge pull request #43 from enjoy-digital/EfficencyFixes 
Bank valid/ready refactor
 2018-09-23 09:40:14 +02:00
John Sully 8447d69326 We wait an extra cycle for no reason 2018-09-23 01:29:19 +02:00
John Sully c4bd842cdf Fix many bugs 2018-09-23 01:21:18 +02:00
John Sully fa0f3b2777 Use the ready signal for cas_allowed so that arbitrators know not to iterate 2018-09-22 17:15:19 +02:00
Florent Kermarrec c12404e00c README: Add ECC 2018-09-19 11:42:13 +02:00
Florent Kermarrec 3f4c14b068 frontend/ecc: expose incident bits, change clear register name 2018-09-19 11:33:49 +02:00
Florent Kermarrec b9aadf11d1 frontend/axi: remove write buffer reservation (not needed) 2018-09-19 10:53:40 +02:00
Tim 'mithro' Ansell ea1ac4d6d7 s6ddrphy: Pass missing nranks parameter. 
Fixes #41.
 2018-09-18 16:58:07 -07:00
Florent Kermarrec e5696ad3ef frontend/ecc: add enable csr 2018-09-18 19:30:08 +02:00
Florent Kermarrec e6ef89a4d3 frontend/axi: optimize burst2beat timings 2018-09-18 19:15:40 +02:00
Florent Kermarrec 6941285d3f frontend/ecc: split Write/Read path and add buffer to improve timings 2018-09-18 17:23:18 +02:00
Florent Kermarrec 041817df7a frontend/ecc: use csr instead of signal for control 2018-09-18 16:23:54 +02:00
Florent Kermarrec b145b0c338 frontend/axi: fix write response implementation 2018-09-18 15:24:41 +02:00
Florent Kermarrec d23dbf6e57 phy: add nranks to all phys 2018-09-17 09:07:09 +02:00
Florent Kermarrec 461b076624 frontend/ecc: add ecc adapter 2018-09-16 01:01:45 +02:00
Florent Kermarrec c84b58735a frontend: add initial ecc code (still need to be integrated) 
Works but all combinatorial, will maybe need to be pipelined
 2018-09-15 23:37:59 +02:00
Florent Kermarrec a8d26724dd phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation 2018-09-15 02:22:12 +02:00
Florent Kermarrec 5719d71ace phy/s7ddrphy_halfrate_bl8: fix cs_n 2018-09-15 00:47:33 +02:00
Florent Kermarrec 36fa324291 core/multiplexer: fix regression (introduced by multirank support) 2018-09-12 07:14:59 +02:00
Florent Kermarrec 42d0e5bbaa core/multiplexer: add more information on odt fixme 2018-09-10 16:34:18 +02:00
Florent Kermarrec 919b756261 phy/model: pass nranks to Interface 2018-09-10 15:17:07 +02:00
Florent Kermarrec f5c7b61704 multirank: set default nranks to 1 if not specified 2018-09-10 15:16:46 +02:00
Florent Kermarrec f3d403f1e0 s7ddrphy: fix typo (reset_n --> cs_n) 2018-09-10 04:44:35 +02:00
Florent Kermarrec 37f1decfb2 multirank: one cs_n/cke/odt/clk per rank 2018-09-09 14:32:15 +02:00
Florent Kermarrec 3e17d18b0c phy: add halfrate_bl8 variant for s7ddrphy 2018-09-09 03:30:18 +02:00
enjoy-digital 412e9a5c51
Merge pull request #38 from enjoy-digital/multirank 
Multirank
 2018-09-09 02:03:20 +02:00
Florent Kermarrec 8ddc6c735d drive odt of all ranks, fixes and test non regression with 1 rank 2018-09-09 01:52:24 +02:00
enjoy-digital d9c243037a
Merge pull request #36 from JohnSully/timing_1 
Fix failing timing
 2018-09-08 13:17:26 +02:00
efd7a47890 Fix failing timing 2018-09-07 22:12:24 -04:00
Florent Kermarrec d4f434da3d dfii: send command to all ranks 2018-09-07 18:40:46 +02:00
Florent Kermarrec b1c2739305 initial multirank support (nbankmachines = nranks * (2**bankbits)) 
To see:
Configure the 2 ranks. (init commands, leveling)
How to drive ODT?
Pipeline stall while switching ranks?
 2018-09-07 18:34:08 +02:00
Florent Kermarrec cc481be81f examples: add sdram_rank_nb and user_ports_id_width 2018-09-07 17:55:46 +02:00
Florent Kermarrec 849b1f6c35 frontend/axi: generate rlast signal 2018-09-06 11:11:17 +02:00
Florent Kermarrec 1fa73e4718 test: update 2018-09-06 11:10:45 +02:00
Florent Kermarrec 7b61b68f68 sdram_init: min value for wr is 5 2018-09-05 23:40:04 +02:00
Florent Kermarrec 1652ab95c8 examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) 2018-09-05 09:13:47 +02:00
Florent Kermarrec 1e64b7f492 examples/litedram_gen: expose resp signals to user 2018-09-05 08:51:27 +02:00
Florent Kermarrec 700f76c599 frontend/axi: add resp signals 2018-09-05 08:50:28 +02:00
Florent Kermarrec 47fed1b254 frontend/axi: add last limitation 2018-09-05 08:33:49 +02:00
Florent Kermarrec de69867995 examples/litedram_gen: expose last signals to user 2018-09-05 08:32:49 +02:00
Florent Kermarrec e8bd782999 examples/litedram_gen: expose burst signals to user 2018-09-05 08:31:57 +02:00
Florent Kermarrec e1598ceee8 phy/s7ddrphy: fix BL8 assert 2018-09-04 09:34:10 +02:00
Florent Kermarrec ebba39d928 README: update 2018-09-03 14:18:35 +02:00
Florent Kermarrec e528e92b9b phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) 2018-09-03 14:06:04 +02:00