Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
651 Commits 6 Branches 14 Tags 3.8 MiB
Commit Graph

651 Commits

Author SHA1 Message Date
Florent Kermarrec bbdd6835aa mac/crc: Cleanup and try to move data-path connection outside of FSM for timings. 2024-03-26 11:55:13 +01:00
Florent Kermarrec b22ac619ab mac/crc: Avoid dummy CRC classes since we only have one CRC Engine implementation. 2024-03-26 11:36:43 +01:00
Florent Kermarrec 95ff76867f mac/crc: Rename dw to data_width. 2024-03-26 11:30:07 +01:00
Florent Kermarrec 01abb2a60f mac/crc/LiteEthMACCRC32: Rename last_be to be and add comments. 2024-03-26 11:28:09 +01:00
Florent Kermarrec 5fad30cbc9 mac/crc/LiteEthMACCRC32: Simplify last_be using reset value and merge for loops. 2024-03-26 11:07:06 +01:00
Florent Kermarrec d9f7ae4882 mac/crc: Another cleanup pass. 2024-03-26 10:50:49 +01:00
Florent Kermarrec aded91f8cb mac/crc: Add optmize_xors method and better signal names. 2024-03-26 10:25:22 +01:00
Florent Kermarrec 1720050729 mac/crc: Switch to LiteXModule, LiteX's Reduce and avoid OrderedDict (no longer required). 2024-03-26 09:59:22 +01:00
Florent Kermarrec 4af0c77371 phy/a7_1000basex: Switch txoutclk buffer to BUFG. 2024-03-25 16:00:39 +01:00
Florent Kermarrec 292551a0f1 phy/a7_1000basex: Add parameters to allow selecting TX/RX Clock Managment Modules (PLL or MMCM) and buffer types. 
This is useful when using multiple instance in the design to optimize/select resources and allow build.
 2024-03-22 12:28:24 +01:00
Florent Kermarrec 1a5d93509b liteeth_gen: Allow selection QPLL channel on Artix7 through qpll_channel parameter. 2024-03-19 17:56:13 +01:00
Florent Kermarrec 5eb986b004 liteeth_gen: Allow external QPLL on Artix7 to allow multiple PHYs per Quad. 
Requires setting qpll parameter to False in .yml config file.
 2024-03-18 14:24:32 +01:00
Florent Kermarrec 0914fb5e51 liteeth_gen: Add optional --name parameter to configure generated verilog name. 2024-03-18 13:49:45 +01:00
Florent Kermarrec 2c67d13456 examples: Improve identation/presentation. 2024-03-18 13:43:11 +01:00
Florent Kermarrec e3a5d6fc19 phy/pcs_1000basex: Expose timers to ease debug. 2024-03-04 16:19:08 +01:00
Florent Kermarrec ab4606c5a1 phy/1000basex: Expose pcs, tx_init and rx_init modules to ease debug. 2024-03-04 16:17:39 +01:00
Florent Kermarrec 3061bf91ce liteeth_gen: Make udp_ports definition optional in .yml file (ex for configuration with only Etherbone). 2024-02-29 14:56:52 +01:00
Florent Kermarrec 21ff1b9369 liteeth_gen: Remove unwanted data_width assertion on Etherbone. 2024-02-29 14:49:37 +01:00
Florent Kermarrec b4e2850623 phy/Ultrascale/1000BaseX: Configure PROGDIV_CFG from linerate. 2024-02-07 11:34:01 +01:00
Florent Kermarrec 80ba793bcf phy/Ultrascale/1000BaseX: Switch to LiteICLink's ChannelPLL for more flexibility/simplicity. 
LiteICLink's ChannelPLL directly computes the CPLL/DIV parameters.
 2024-02-07 09:24:01 +01:00
Florent Kermarrec 8f521d838c liteeth_gen: Finish Artix7 2500BaseX integration. 2024-02-06 18:26:54 +01:00
Florent Kermarrec 1fefe49e74 README: List 2500BaseX support. 2024-01-23 15:57:00 +01:00
Florent Kermarrec dd2ecfefd8 liteeth/phy: Add USP_GTY_2500BASEX support. 2024-01-23 15:55:25 +01:00
Florent Kermarrec fec0e23eb1 liteeth/phy: Add USP_GTH_2500BASEX support. 2024-01-23 15:50:01 +01:00
Florent Kermarrec 664a633d29 liteeth/phy: Fix 2500basex linerate. 2024-01-23 15:44:33 +01:00
Florent Kermarrec 4527e8137e liteeth/phy: Add KU_2500BASEX support. 2024-01-23 15:42:01 +01:00
Florent Kermarrec 3e8dbe23ef liteeth/phy: Add K7_2500BASEX support. 2024-01-23 15:38:48 +01:00
Florent Kermarrec 19c555171b liteeth_phy: Merge a7_2500basex in a7_1000basex and handle changes through linerate. 2024-01-23 15:23:51 +01:00
Florent Kermarrec 5a1caed75f liteeth_gen: Add A7_2500BASEX support. 2024-01-23 13:54:06 +01:00
Florent Kermarrec a00c9a3d22 liteeth_gen: Add TX/RX polarity support to SGMII/1000BASEX PHYs. 2024-01-23 12:45:48 +01:00
Florent Kermarrec 3b10143da2 liteeth_gen: Fixes on Artix7 integration. 2024-01-22 19:49:30 +01:00
Gwenhael Goavec-Merou 650433dd4b phy/gw5rgmii: fix clks assignment 2024-01-22 06:38:16 +01:00
Florent Kermarrec 95081445e7 liteeth_gen/A7_1000BASEX: Add support for 156.25MHz refclk_freq and fix 200MHz to 125MHz. 2024-01-19 21:40:45 +01:00
Florent Kermarrec c05de191e2 liteeth_gen: Add specific A7_1000BASEX support and example configuration. 
Adapted from known working targets but untested on hardware.
 2024-01-18 13:27:32 +01:00
Gwenhael Goavec-Merou 1ea28bd93a phy/gw5rgmii: avoid synthesis noise by adding missing in/out ports for IODELAY primitives 2024-01-08 07:26:35 +01:00
Florent Kermarrec 1c9acfeaa7 setup.py: Fix/Revert classifiers. 2024-01-01 15:27:37 +01:00
Florent Kermarrec a4b74c32c1 setup.py: Bump to 2023.12 to prepare release. 2023-12-25 15:34:01 +01:00
Florent Kermarrec d3a05ae631 setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguments in functions). 2023-12-19 10:24:18 +01:00
Florent Kermarrec 6ec993650c setup.py: Specify UTF-8 encoding for long_description/README.md. 2023-12-19 10:12:51 +01:00
Florent Kermarrec 0ae737956d setup.py: Improve indentation. 2023-12-19 09:10:32 +01:00
Florent Kermarrec 4eec8419d0 test/test_model: Update EtherbonePacket. 2023-11-10 16:14:26 +01:00
Florent Kermarrec f3f0486990 CONTRIBUTORS: Update. 2023-11-10 10:41:51 +01:00
enjoy-digital fc190e8f7b
Merge pull request #149 from trabucayre/etherbone_hybrid 
core/__init__: LiteEthUDPIPCore, LiteEthIPCore: expose interface & endianness at LiteEthUDPIPCore constructor. LiteEthIPCore: don't hardcode interface, pass macaddr and endianness to LiteEthMAC
 2023-10-23 18:33:46 +02:00
Gwenhael Goavec-Merou daf1a1ac63 core/__init__: LiteEthUDPIPCore, LiteEthIPCore: expose interface & endianness at LiteEthUDPIPCore constructor. LiteEthIPCore: don't hardcode interface, pass macaddr and endianness to LiteEthMAC 2023-10-23 16:18:28 +02:00
Florent Kermarrec 09d31b5af8 core/arp: Fix mem_wr_port alias direction. 2023-10-13 14:31:03 +02:00
Florent Kermarrec 9d13f612c1 core/arp: Fix missing set of response.mac_address in UPDATE_TABLE and reset update_count at the end of CLEAR state. 
Fixes #147.
 2023-10-11 09:09:02 +02:00
Florent Kermarrec e784bf8fd3 core/arp: Use signals for alias to simplify debug. 2023-10-11 09:03:19 +02:00
Florent Kermarrec 79600f954a mac/sram: Minor cleanup by directly using port instead of ports[n] in the loop. 2023-10-10 14:55:26 +02:00
Gwenhael Goavec-Merou 8b2bd00a95 mac/sram: LiteEthMACSRAMReader: force READ_FIRST for mems ports (fix tx packet corruption for efinix trion/titanium) 2023-10-10 14:49:44 +02:00
Florent Kermarrec 42772f4388 setup.py: Update to 2023.08. 2023-09-18 08:42:17 +02:00