In some hardware, ref_clk can be input for both the MAC and the PHY. In this
case, setting refclk_cd to None will make the CRG use ref_clk as the RMII
input reference clock:
Pads:
# RMII Ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("F16")),
Subsignal("rx_data", Pins("A20 B18")),
Subsignal("crs_dv", Pins("C20")),
Subsignal("tx_en", Pins("A19")),
Subsignal("tx_data", Pins("C18 C19")),
Subsignal("mdc", Pins("F14")),
Subsignal("mdio", Pins("F13")),
Subsignal("rx_er", Pins("B20")),
Subsignal("int_n", Pins("D21")),
IOStandard("LVCMOS33")
),
PHY:
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
refclk_cd = None)
Thanks @mwick83 for reporting the use case and for the initial implementation.
This ensures the full Etherbone packet is available before starting the transmission
and fixes transmission issues with larges bursts or slow sys_clk_freq.
For correct io delays in nextpnr the DEL_VALUE parameter needs to
be an integer, instead of the "DELAY{}" string.
The use of a "DELAY{}" string appears in the Lattice primitive
manual, but appears to be incorrect. At least based of the current
nextpnr.
Because we are not making use of dynamic io delays here we can
also use the simpler DELAYG block instead of DELAYF.
Fixes#50
On ECP5 targets the core struggles to meet timing closure. This
change adds buffers to the CRC module on tx/rx paths.
This results in 20-30MHz gain to max clock rate.
This fixes#47
Previously, it would fail with:
$ liteeth/gen.py examples/wishbone_mii.yml
[snip]
Traceback (most recent call last):
File "liteeth/gen.py", line 346, in <module>
main()
File "liteeth/gen.py", line 331, in main
soc = MACCore(platform, core_config)
File "liteeth/gen.py", line 244, in __init__
self.add_wb_master(bridge.wishbone)
File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master
self.bus.add_master(master=wbm)
File "[...]/litex/soc/integration/soc.py", line 347, in add_master
master = self.add_adapter(name, master, "m2s")
File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter
bridge_cls = {
KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)
This makes clocking more flexible and allows routing on more boards (ex: Pano Logic G2). Since TX clocking
does not need clock phase relationship with the input clock using a combinatorial path is fine.
This makes it Xilinx specific, but without it ISE simplifies this as a single signal
(which is fine) but is not able to keep track of the "keep" attribute of both signals
and fails applying the constraints.
