540ad8c9dc
liteeth/mac: use native dw for LiteEthMACWishboneInterface
...
This is required to support 64-bit wide data paths using the automatic
Wishbone bus width conversion as discussed in
enjoy-digital/liteeth#75 . Otherwise, if the MAC data width deviates
from the 32-bit default set previously, received and transmitted
packets will be broken.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-10-13 17:47:28 +02:00
8ecc3ca6d9
mac/core: Disable Preamble/CRC with LiteEthPHYModel.
2021-10-05 15:41:44 +02:00
5276a7543f
mac/core: Split add_converter in add_cdc/add_converter/add_last_be.
2021-10-05 15:32:49 +02:00
a4a070af4d
mac/core: Introduce TX/RXDatapath modules to simplify code.
2021-10-05 15:13:08 +02:00
11555d43cb
mac/core: Avoid passing core_dw/phy_dw to add_tx/rx_converter.
2021-10-05 14:20:22 +02:00
6204994bad
common: Define eth_min_frame_length, eth_fcs_length and arp_min_length and use them in core/mac/model.
2021-10-05 14:10:41 +02:00
944849c3cf
mac/core: Move CSRs to top and rename dw to datapath_dw.
2021-10-05 13:59:22 +02:00
821f725d58
mac/core: Improve modules's names: tx_xy/rx_xy everywhere.
2021-10-05 13:48:56 +02:00
511ba001dc
mac/core: Avoid reversed order for TX path now that separated from RX path.
2021-10-05 11:52:11 +02:00
6901d418b3
mac/core: Split TX/RX parts and cleanup to improve readability/maintenance.
2021-10-05 11:39:56 +02:00
7ed1c61237
mac/core: Cosmetic cleanups.
2021-10-05 10:33:23 +02:00
ce8523f31b
mac: Rename sys_datapath to with_sys_datapath.
2021-10-05 10:23:01 +02:00
a00a200547
mac/sram: Cleanup/Simplify LiteEthMACSRAMReader.
...
- Improve signal names.
- Use re on memories to simplify addressing (still need to anticipate read by 1 cycle).
Also do minor cleanups to LiteEthMACSRAMWriter.
2021-10-05 09:52:46 +02:00
89dbf17cb6
mac/sram: Cleanup/Simplify LiteEthMACSRAMWriter.
...
- Improve signal names.
- Avoid IDLE State.
- Also check for error when length > eth_mtu.
- Use int(math.log2()) instead of log2_int.
2021-10-01 19:56:10 +02:00
1685c56100
mac/sram: Avoid last_be encoding/decoding generalization.
...
We now only have to handle 2 cases (32-bit/64-bit) and code is easier to
apprehend with the direct mapping.
2021-10-01 19:12:59 +02:00
e794459946
mac: Move sram dw/sram checks to LiteEthMAC.
2021-10-01 18:30:37 +02:00
692df29981
mac/sram: Move LastBEDecoder/LastBEEncoder.
2021-10-01 18:27:10 +02:00
717885eb0a
mac: Update copyrights.
2021-10-01 18:18:00 +02:00
cab4e93317
mac/wishbone: Remove internal data-width conversion added by #75 to let LiteX handle it directly.
...
LiteX integration is already able to automatically convert bus data-width: When adding a 64-bit peripheral
to 32-bit SoC, the adapters will automatically be inserted.
When SRAM dw is 64-bit for a 32-bit SoC, automatic convertion can be seen in the build log:
INFO:SoCBusHandler:ethmac Region allocated at Origin: 0x80000000, Size: 0x00002000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:ethmac Bus converted from Wishbone 64-bit to Wishbone 32-bit.
INFO:SoCBusHandler:ethmac added as Bus Slave.
INFO:SoCIRQHandler:ethmac IRQ allocated at Location 2.
Also fix copyright order.
2021-10-01 18:11:41 +02:00
aafb7081ff
mac: Disable sys_data_path by default since seems to introduce a regression.
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netboot no longer works on Arty with sys_data_path set to True:
python3 -m litex_boards.targets.digilent_arty --with-ethernet --build
2021-10-01 16:22:33 +02:00
f50f6d242c
Merge pull request #82 from david-sawatzke/endianconversion_sram
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mac/sram: Handle endianness only in sram
2021-10-01 15:49:43 +02:00
71cb365bc5
mac/sram: Handle endianness only in sram
2021-09-29 18:35:19 +02:00
40f22569a7
Merge pull request #77 from david-sawatzke/64bitmacpath
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Add 64 bit support to mac pipeline
2021-09-27 17:28:03 +02:00
6fbb10abfb
Merge pull request #75 from lschuermann/dev/sram-wishbone-adjdw
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mac/{sram,wishbone}: remove assumptions about 32-bit dw and add SRAM to Wishbone dw conversion
2021-09-27 17:25:27 +02:00
7847f72c6b
Merge pull request #74 from david-sawatzke/32bitmacpath
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Add toggleable 32 bit support to mac pipeline
2021-09-27 17:22:51 +02:00
8733aecf89
liteeth_gen: Minor cleanups/simplifications.
2021-09-27 17:12:14 +02:00
5358234720
liteth_gen: Remove calls to add_csr (no longed required).
2021-09-27 17:02:23 +02:00
bdff760128
Merge pull request #81 from ozbenh/gen-py-fixes
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gen.py fixes
2021-09-27 17:00:17 +02:00
734d948665
Merge pull request #78 from lschuermann/dev/phy-gmii-model
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phy/gmii: add model parameter to skip clock buffers & generation
2021-09-27 16:58:26 +02:00
bcb1946711
Merge pull request #76 from lschuermann/dev/xgmii-phy
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Add 64-bit XGMII PHY implementation for 10G Ethernet
2021-09-27 16:53:29 +02:00
62855e14f6
mac/wishbone: support smaller Wishbone data width than SRAM dw
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Adds a wishbone.Converter between the SRAM Wishbone slave and the
wishbone.Decoder connected to the SoC bus, to support SRAM data widths
larger than the system bus Wishbone data width. This is important to
be able to run a 32-bit SoC with a 64-bit MAC data path and SRAM
storage.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-27 08:26:06 +02:00
e6a4c2a2f6
mac/sram: support data widths larger than 32 bit
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This removes various assumptions about having a 32 bit data width in
the SRAM module. Especially the last_be encoding and decoding have
been seperated into a module, which generates the one-hot encodings
and decodings on the fly.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-27 08:26:06 +02:00
63ff6f47e7
gen: Add clock constraints
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Otherwise the generated verilog is missing necessary "keep" attributes
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-24 12:19:10 +10:00
f2032a4227
Remove clock asserts
...
They aren't strictly necessary, especially since the MAC can have
a wider data path and thus cope with running slightly slower
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-23 12:24:58 +10:00
1db5299a62
core/ip: Simplify.
2021-09-22 18:59:48 +02:00
e2eb74f704
core/icmp: Simplify.
2021-09-22 18:36:03 +02:00
33322ad80f
core/arp: Simplify IDLE state.
2021-09-22 18:35:48 +02:00
4cadf912f2
bench/arty:bench/arty: Add UDP Streamer example with UDP TX stream from Switches.
2021-09-22 18:21:20 +02:00
c7aa4e50f4
frontend/stream/LiteEthStream2UDPTX: Fix/Simplify no FIFO case.
2021-09-22 18:05:59 +02:00
a26608f30f
bench/arty: Add UDP Streamer example with UDP RX stream redirected to Leds.
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Tested with:
./arty.py --build --load
./test_udp_streamer.py --leds
2021-09-22 17:06:27 +02:00
a6298975bd
core/udp: Simplify LiteEthUDPTX.
2021-09-22 16:54:41 +02:00
8f05e72f99
frontend/etherbone: Simplify code.
2021-09-22 16:45:37 +02:00
bee34ee955
core/udp: Simplify LiteEthUDPRX and make sure to drop exceeding payload.
2021-09-22 16:32:47 +02:00
9b3837e636
Allow "device" to be specified in yaml
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Otherwise we don't get the DDROutput overrides and the standalone
core fails to generate when using GMII_MII
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-22 22:27:30 +10:00
cccc0c720a
Add support for GMII_MII PHY to gen.py
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It was missing. It's useful for Wukong
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-22 22:27:25 +10:00
393158f2a5
frontend/stream/LiteEthUDP2StreamRX: Pass last signal from Sink to Source.
2021-09-22 12:05:09 +02:00
9b88c0f299
frontend/stream: Apply convert_ip to ip_address.
2021-09-22 11:14:01 +02:00
27a0b99e54
common: Improve convert_ip to automatically detect passed format.
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Simplify use in the code.
2021-09-22 11:13:33 +02:00
e39fec240b
CONTRIBUTORS: Update.
2021-09-15 14:49:06 +02:00
8e059b5124
phy/s6rgmii: Remove IBUF (ISE seems to have trouble with it).
2021-09-13 19:31:29 +02:00
Leon Schuermann
Florent Kermarrec
David Sawatzke
Benjamin Herrenschmidt